BR24C01A-W 데이터 시트보기 (PDF) - ROHM Semiconductor

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BR24C01A-W

I2C BUS compatible serial EEPROM

ROHM Semiconductor 

Memory ICs

BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /

BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W

(4) Device addressing

– BR24C01A-W / AF-W / AFJ-W / AFV-W, BR24C02-W / F-W / FJ-W / FV-W

1) Make sure the slave address is output from the master immediately after the start condition.

2) The upper four bits of the slave address are used to determine the device type. The device code for this IC is

fixed at “1010”.

3) The next three bits of the slave address (A2, A1, A0 … device address) are used to select the device. This IC

can address up to eight devices on the same bus.

4) The lowermost bit of the slave address (R / W … READ / WRITE) is used to set the write or read mode as follows.

R / W set to 0 … Write

(Random read word address setting is also 0)

R / W set to 1 … Read

1010

A2

A1

A0

R/W

– BR24C04-W / F-W / FJ-W / FV-W

1) Make sure the slave address is output from the master in continuation with the start condition.

2) The upper four bits of the slave address are used to determine the device type. The device code for this IC is

fixed at “1010”.

3) The next two bits of the slave address (A2, A1, … device address) are used to select the device. This IC can

address up to four devices on the same bus.

4) The next bit of the slave address (PS … Page Select) is used to select the page. As shown below, it can write to

or read from any of the 256 words in the two pages in memory.

PS set to 0 … Page 1 (000 to 0FF)

PS set to 1 … Page 2 (100 to 1FF)

5) The lowermost bit of the slave address (R / W … READ / WRITE) is used to set the write or read mode as follows.

R / W set to 0 … Write

(Random read word address setting is also 0)

R / W set to 1 … Read

1010

A2

A1

PS

R/W

(5) Write protect (WP)

When WP pin set to VCC (High level), write protect is set by all address. When WP pin set to GND (Low level),

enable to write to all address. Either control this pin or connect to GND (or VCC). It is inhibited from being left

unconnected.

(6) ACK signal

The acknowledge signal (ACK signal) is determined by software and is used to indicate whether or not a data transfer

is proceeding normally. The transmitting device, whether the master or slave, opens the bus after an 8-bit data

output (µ-COM when a write or read command of the slave address input ; this IC when reading data).

For the receiving device during the ninth clock cycle, SDA is set to LOW and an acknowledge signal (ACK signal) is

sent to indicate that it received the 8-bit data (this IC when a write command or a read command of the slave address

input, µ-COM when a read command data output).

The ICs output a LOW acknowledge signal (ACK signal) after recognizing the start condition and slave address (8

bits).

When data is being write to the ICs, a LOW acknowledge signal (ACK signal) is output after the receipt of each eight

bits of data (word address and write data).

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