PIC12CE518-04-JW_97 데이터 시트보기 (PDF) - Microchip Technology

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PIC12CE518-04-JW_97

8-Pin, 8-Bit CMOS Microcontroller with EEPROM Data Memory

Microchip Technology 

4.0 MEMORY ORGANIZATION

PIC12CE5XX memory is organized into program mem-

ory and data memory. For devices with more than 512

bytes of program memory, a paging scheme is used.

Program memory pages are accessed using one STA-

TUS register bit. For the PIC12CE519 with a data

memory register file of more than 32 registers, a bank-

ing scheme is used. Data memory banks are accessed

using the File Select Register (FSR).

4.1 Program Memory Organization

The PIC12CE5XX devices have a 12-bit Program

Counter (PC) capable of addressing a 2K x 12

program memory space.

Only the first 512 x 12 (0000h-01FFh) for the

PIC12CE518 and 1K x 12 (0000h-03FFh) for the

PIC12CE519 are physically implemented. Refer to

Figure 4-1. Accessing a location above these

boundaries will cause a wrap-around within the first

512 x 12 space (PIC12CE518) or 1K x 12 space

(PIC12CE519). The effective reset vector is at 000h,

(see Figure 4-1). Location 01FFh (PIC12CE518) or

location 03FFh (PIC12CE519), the hardwired reset

vector location, contains the internal clock oscillator

calibration value. This value is set at Microchip and

should never be overwritten.

Upon reset, the

MOVLW XX is executed, the PC wraps to location

0000h, thus making 0000h the effective reset vector.

PIC12CE5XX

FIGURE 4-1:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC12CE5XX

PC<11:0>

CALL, RETLW

12

Stack Level 1

Stack Level 2

Reset Vector (note 1)

0000h

On-chip Program

Memory

512 Word (PIC12CE518)

On-chip Program

Memory

01FFh

0200h

1024 Word (PIC12CE519) 03FFh

0400h

7FFh

Note 1: Address 0000h becomes the

effective reset vector. Location

01FFh (PIC12CE518) or location

03FFh (PIC12CE519) contains the

MOVLW XX INTRC oscillator

calibration value.

© 1997 Microchip Technology Inc.

Preliminary

DS40172A-page 11

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