CMX605(1999) 데이터 시트보기 (PDF) - MX-COM Inc
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CMX605 Datasheet PDF : 22 Pages
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Digital Line to POTS Interface
9
CMX605 Preliminary Information
MODE Register
Bit 4 Bit 3 Bit 2
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Signal Level Adjustment
(dB)
0
-2
-4
-6
-8
-10
-12
-14
Table 8: Typical Level settings as determined by Bits 2, 3, and 4 of the Mode Register
4.6 Tx UART
This block connects the µC, via the ‘C-BUS’ interface, to the FSK Encoder.
The block can be programmed to convert transmit data from 8-bit bytes to asynchronous data characters by
adding Start and Stop bits. The transmit data is then passed to the FSK Encoder.
Data to be transmitted should be loaded by the µC into the TX DATA Register when the Tx Data Ready bit (bit
6) of the STATUS Register goes high. The data will then be treated by the Tx UART block in one of two ways,
depending on the setting of bit 1 of the SETUP Register:
If bit 1 of the SETUP Register is ‘0’ (Tx Sync mode) then the 8 bits from the TX DATA Register will be
transmitted sequentially at 1200bps, LSB (D0) first.
If bit 1 of the SETUP Register is ‘1’ (Tx Async mode) then bits will be transmitted as asynchronous data
characters at 1200bps according to the following format:
One Start bit (Space)
Eight Data bits (D0-D7) from the TX DATA Register, with the LSB (D0) transmitted first
One Stop bit (Mark)
Failure to load the TX DATA Register with a new value when required will result in bit 7 (Tx Data Underflow)
of the STATUS Register being set to ‘1’. If the ‘Tx Async’ mode of operation is selected then a continuous
Mark (‘1’) signal will be transmitted until a new value is loaded into TX DATA. If the ‘Tx Sync’ mode is selected
then the byte already in the TX DATA Register will be re-transmitted.
Tx FSK signal:
TTBD
TX DATA Register loaded:
Tx Data Ready flag bit:
Tx Data Underflow flag bit:
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop Start D0
TTBD
TTBD
Figure 3: Transmit UART Function (Async)
4.7 DTMF Tone Decoder
This block is enabled or disabled by bit 5 of the SETUP register. If disabled, bit 0 to bit 5 of the STATUS
Register are set to ‘0’ and no interrupts are generated. When enabled (set to ‘1’), a status change of the
decoder will generate an interrupt and bit 5 of the STATUS Register will be set to ‘1’. The validity of the data
is indicated by bit 4 of the STATUS Register. The decode truth table is shown in
Table 9.
©1999 MX-COM, Inc.
www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054
Doc. # 20480195.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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