74HC32-Q100 데이터 시트보기 (PDF) - NXP Semiconductors.

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74HC32-Q100

Quad 2-input OR gate

NXP Semiconductors. 

NXP Semiconductors

74HC32-Q100; 74HCT32-Q100

Quad 2-input OR gate

5. Pinning information

5.1 Pinning

+&4

+&74

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*1' 

 9&&

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DDD

Fig 4. Pin configuration SO14 and TSSOP14

5.2 Pin description

Table 2.

Symbol

1A to 4A

1B to 4B

1Y to 4Y

GND

VCC

Pin description

Pin

1, 4, 9, 12

2, 5, 10,13

3, 6, 8, 11

7

14

Description

data input

data input

data output

ground (0 V)

supply voltage

6. Functional description

Table 3. Function table[1]

Input

nA

nB

L

L

L

H

H

L

H

H

[1] H = HIGH voltage level;

L = LOW voltage level;

X = don’t care.

+&4

+&74

WHUPLQDO 

LQGH[ DUHD

% 

< 

$ 

% 

< 

*1'

 %

 $

 <

 %

 $

DDD

7UDQVSDUHQW WRS YLHZ

(1) The die substrate is attached to this pad using

conductive die attach material. It cannot be used as a

supply pin or input.

Fig 5. Pin configuration DHVQFN14

Output

nY

L

H

H

H

74HC_HCT32_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 1 August 2012

© NXP B.V. 2012. All rights reserved.

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