S25FL032P 데이터 시트보기 (PDF) - Cypress Semiconductor
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S25FL032P Datasheet PDF : 60 Pages
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S25FL032P
6. SPI Modes
A microcontroller can use either of its two SPI modes to control Cypress SPI Flash memory devices:
CPOL = 0, CPHA = 0 (Mode 0)
CPOL = 1, CPHA = 1 (Mode 3)
Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for both modes.
When the bus master is in standby mode, SCK is as shown in Figure 8 for each of the two modes:
SCK remains at 0 for (CPOL = 0, CPHA = 0 Mode 0)
SCK remains at 1 for (CPOL = 1, CPHA = 1 Mode 3)
Figure 7. Bus Master and Memory Devices on the SPI Bus
SO
SPI Interface with
SI
(CPOL, CPHA) =
(0, 0) or (1, 1)
SCK
Bus Master
SCK SO SI
Design SCK SO SI
SCK SO SI
d for New CS3 CS2 CS1
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS#
HOLD#
W#/ACC
CS#
HOLD#
W#/ACC
CS#
HOLD#
W#/ACC
ende Note
m The Write Protect/Accelerated Programming (W#/ACC) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate.
om Figure 8. SPI Modes Supported
ec CS#
R CPOL CPHA
Not Mode 0 0
0 SCK
Mode 3 1
1 SCK
SI
MSB
SO
MSB
Document Number: 002-00650 Rev. *L
Page 10 of 60
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