WM8804_09 데이터 시트보기 (PDF) - Cirrus Logic
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WM8804_09 Datasheet PDF : 66 Pages
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Production Data
CONTROL INTERFACE – 3-WIRE MODE
WM8804
t CSS
CSB
tCSU
tSCY
SCLK
SDIN
SDO
t DSU
t DHO
t DL
tCSM
t CSH
t SCS
t SCR
LSB
LSB
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
Program Register Input Information
SCLK rising edge to CSB rising edge
tSCS
60
SCLK cycle time
tSCY
80
SCLK duty cycle
40/60
60/40
SDIN to SCLK set-up time
tDSU
20
SDIN hold time from SCLK rising edge
tDHO
20
SDOUT propagation delay from SCLK rising edge
tDL
5
CSB pulse width high
tCSH
20
SCLK to CSB low (required for read cycle) set-up time
tCSU
20
CSB min (write cycle only)
tCSM
0.5* tSCY
SCLK fall to CSB high
tCSR
20
CSB rising/falling to SCLK rising
tCSS
20
SCLK glitch suppression
tps
2
8
Table 4 Control Interface Timing – 3-Wire Serial Control Mode
UNIT
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
w
PD, Rev 4.5, March 2009
9
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