CDB5343 데이터 시트보기 (PDF) - Cirrus Logic

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CDB5343

CDB5343: Evaluation Board for CS5343

Cirrus Logic 

CDB5343

The CS5343 generates sub-clocks when it is set for Master Mode via DIP switch S1. In this scenario, the

CS8406 should be set to Slave Mode to receive sub-clocks. Similarly, the “SCLK, LRCK” switch should

be closed to direct sub-clocks to the header. The sub-clock output of the J3 header is fixed at 3.3 V.

If the user configures the CS5343 for Slave Mode, the device must receive sub-clocks either from the

CS8406 or from an external source via header J3. If the CS8406 is the intended sub-clock source, DIP

switch S1 must be set such that the CS8406 is in Master Mode and “SCLK, LRCK” are routed to the head-

er. If both the CS5343 and the CS8406 are set to Slave Mode, DIP switch S1 must indicate that the sub-

clocks come “FROM HDR.” Sub-clock input to header J3 may be either 3.3 V or 5 V.

4.1.3

Data Routing

Audio data from the CS5343 SDOUT pin is routed to header J3 and the CS8406. The SDOUT pin of J3

is always a 3.3 V output. The CS5343 produces data in only I²S audio format; therefore the data capture

device should be set accordingly.

The CS8406 accepts data in I²S audio format, which it converts to S/PDIF and EIAJ-340-compatible data.

This data is available for capture from either the optical connector (J9) or the RCA jack (J6).

5. POWER

Power must be supplied to the evaluation board through the +5 V binding post (J2). The +5 V input must be refer-

enced to the single black binding post ground connector (J1).

WARNING: Please refer to the CS5343 data sheet for allowable voltage levels.

6. GROUNDING AND POWER SUPPLY DECOUPLING

To optimize performance, PCB designs supporting the CS5343 require careful attention to power supply, grounding,

and signal routing. Figures 26 and 27 show the basic component/signal interconnect for the CDB5343, and

Figure 25 shows the component placement. These figures demonstrate the optimal layout of components used to

support the CS5343. For example, these figures show that the decoupling capacitors are located as close to the

CS5343 as possible. The layout also shows extensive use of ground plane fill which greatly reduces radiated noise.

7. ANALOG INPUT

The user can input single-ended analog signals via the RCA connectors, J5 and J7. A 2 Vrms single-ended signal

into the RCA connectors will drive the CS5343 inputs to full scale (1 Vrms for VA = 5 V). The input network on the

CDB5343 was designed to demonstrate that the CS5343 will achieve full performance with a source impedance up

to 2.5 kΩ (looking back from the CS5343 inputs) while allowing for 2 Vrms inputs. Another advantage of this circuit

is that it provides an input impedance of 10 kΩ, similar to many commercial audio products.

DS687DB2

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