MC1496D 데이터 시트보기 (PDF) - Motorola => Freescale

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MC1496D

Balanced Modulators/Demodulators

Motorola => Freescale 

MC1496, B

GENERAL OPERATING INFORMATION

Carrier Feedthrough

Carrier feedthrough is defined as the output voltage at

carrier frequency with only the carrier applied (signal

voltage = 0).

Carrier null is achieved by balancing the currents in the

differential amplifier by means of a bias trim potentiometer

(R1 of Figure 5).

Carrier Suppression

Carrier suppression is defined as the ratio of each

sideband output to carrier output for the carrier and signal

voltage levels specified.

Carrier suppression is very dependent on carrier input

level, as shown in Figure 22. A low value of the carrier does

not fully switch the upper switching devices, and results in

lower signal gain, hence lower carrier suppression. A higher

than optimum carrier level results in unnecessary device and

circuit carrier feedthrough, which again degenerates the

suppression figure. The MC1496 has been characterized

with a 60 mVrms sinewave carrier input signal. This level

provides optimum carrier suppression at carrier frequencies

in the vicinity of 500 kHz, and is generally recommended for

balanced modulator applications.

Carrier feedthrough is independent of signal level, VS.

Thus carrier suppression can be maximized by operating

with large signal levels. However, a linear operating mode

must be maintained in the signal–input transistor pair – or

harmonics of the modulating signal will be generated and

appear in the device output as spurious sidebands of the

suppressed carrier. This requirement places an upper limit on

input–signal amplitude (see Figure 20). Note also that an

optimum carrier level is recommended in Figure 22 for good

carrier suppression and minimum spurious sideband

generation.

At higher frequencies circuit layout is very important in

order to minimize carrier feedthrough. Shielding may be

necessary in order to prevent capacitive coupling between

the carrier input leads and the output leads.

Signal Gain and Maximum Input Level

Signal gain (single–ended) at low frequencies is defined

as the voltage gain,

+ + ) + AVS

Vo

VS

RL

Re 2re

where

re

26 mV

I5(mA)

A constant dc potential is applied to the carrier input terminals

to fully switch two of the upper transistors “on” and two

transistors “off” (VC = 0.5 Vdc). This in effect forms a cascode

differential amplifier.

Linear operation requires that the signal input be below a

critical value determined by RE and the bias current I5.

p VS I5 RE (Volts peak)

Note that in the test circuit of Figure 10, VS corresponds to a

maximum value of 1.0 V peak.

Common Mode Swing

The common–mode swing is the voltage which may be

applied to both bases of the signal differential amplifier,

without saturating the current sources or without saturating

the differential amplifier itself by swinging it into the upper

switching devices. This swing is variable depending on the

particular circuit and biasing conditions chosen.

Power Dissipation

Power dissipation, PD, within the integrated circuit package

should be calculated as the summation of the voltage–current

products at each port, i.e. assuming V12 = V6, I5 = I6 = I12

and ignoring base current, PD = 2 I5 (V6 – V14) + I5)

V5 – V14 where subscripts refer to pin numbers.

Design Equations

The following is a partial list of design equations needed to

operate the circuit with other supply voltages and input

conditions.

A. Operating Current

The internal bias currents are set by the conditions at Pin 5.

Assume:

tt I5 = I6 = I12,

IB IC for all transistors

then :

+ ** *f W V

R5

I5

where: R5 is the resistor between

500 where: Pin 5 and ground

where: φ = 0.75 at TA = +25°C

The MC1496 has been characterized for the condition

I5 = 1.0 mA and is the generally recommended value.

B. Common–Mode Quiescent Output Voltage

V6 = V12 = V+ – I5 RL

Biasing

The MC1496 requires three dc bias voltage levels which

must be set externally. Guidelines for setting up these three

levels include maintaining at least 2.0 V collector–base bias

on all transistors while not exceeding the voltages given in

the absolute maximum rating table;

w w 30 Vdc [(V6, V12) – (V8, V10)] 2 Vdc

w w 30 Vdc [(V8, V10) – (V1, V4)] 2.7 Vdc

w w 30 Vdc [(V1, V4) – (V5)] 2.7 Vdc

The foregoing conditions are based on the following

approximations:

V6 = V12, V8 = V10, V1 = V4

Bias currents flowing into Pins 1, 4, 8 and 10 are transistor

base currents and can normally be neglected if external bias

dividers are designed to carry 1.0 mA or more.

Transadmittance Bandwidth

Carrier transadmittance bandwidth is the 3.0 dB bandwidth

of the device forward transadmittance as defined by:

+  + g21C

io (each sideband)

vs (signal)

Vo

0

Signal transadmittance bandwidth is the 3.0 dB bandwidth

of the device forward transadmittance as defined by:

+  + + g21S

io (signal)

vs (signal)

Vc

0.5 Vdc, Vo

0

MOTOROLA ANALOG IC DEVICE DATA

3

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