CAT25010Z 데이터 시트보기 (PDF) - Catalyst Semiconductor => Onsemi

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CAT25010Z

1K/2K/4K SPI Serial CMOS EEPROM

Catalyst Semiconductor => Onsemi 

CAT25010/20/40

DESIGN CONSIDERATIONS

The CAT250140/20/40 powers up in a write disable

state and in a low power standby mode. A WREN

instruction must be issued to perform any writes to the

device after power up. Also,on power up CS should be

brought low to enter a ready state and receive an

instruction. After a successful byte/page write or status

register write, the CAT250140/20/40 goes into a write

disable mode. CS must be set high after the proper

number of clock cycles to start an internal write cycle.

Access to the array during an internal write cycle is

ignored and programming is continued. On power up,

SO is in a high impedance. If an invalid op code is

received, no data will be shifted into the CAT250140/

20/40, and the serial output pin (SO) will remain in a

high impedance state until the falling edge of CS is

detected again.

When powering down, the supply should be taken down

to 0V, so that the CAT250140/20/40 will be reset when

power is ramped back up. If this is not possible, then,

following a brown-out episode, the CAT250140/20/40

can be reset by refreshing the contents of the Status

Register (See Application Note AN10).

Figure 8. Page Write Instruction Timing

CS

012345678

13 14 15 16-23 24-31 16+(N-1)x8-1..16+(N-1)x8 16+Nx8-1

SK

OPCODE

BYTE ADDRESS

DATA IN

SI

0 0 0 0 X0* 0 1 0 A7

Data Data Data

A0 Byte 1 Byte 2 Byte 3

Data Byte N

7..1

0

HIGH IMPEDANCE

SO

Note: Dashed Line= mode (1, 1) – – – – – *X=0 for 25010, 25020 ; X=A8 for 25040

Figure 9. HOLD Timing

CS

SCK

HOLD

SO

tCD

tHD

tHZ

Note: Dashed Line= mode (1, 1) – – – – –

tCD

tHD

HIGH IMPEDANCE

tLZ

9

Doc. No. 1006, Rev. L

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