33887 데이터 시트보기 (PDF) - Motorola => Freescale
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33887 Datasheet PDF : 28 Pages
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Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
PWM Frequency (Note 23)
Maximum Switching Frequency During Active Current Limiting (Note 24)
Output ON Delay (Note 25)
V+ = 14 V
f PWM
–
10
–
kHz
f MAX
–
–
20
kHz
t d (ON)
–
µs
–
18
Output OFF Delay (Note 25)
V+ = 14 V
t d (OFF)
–
µs
–
18
ILIM Output Constant-OFF Time for Low-Side MOSFETs (Note 26), (Note 27)
ta
15
20.5
26
µs
ILIM Blanking Time for Low-Side MOSFETs (Note 28), (Note 27)
tb
12
16.5
21
µs
Output Rise and Fall Time (Note 29)
V+ = 14 V, IOUT = 3.0 A
tf, tr
µs
2.0
5.0
8.0
Disable Delay Time (Note 30)
Power-ON Delay Time (Note 31)
Wake-Up Delay Time (Note 31)
Output MOSFET Body Diode Reverse Recovery Time (Note 32)
t d (disable)
–
–
8.0
µs
t pod
–
1.0
5.0
ms
t wud
trr
–
1.0
5.0
ms
100
–
–
ns
Notes
23. The outputs can be PWM-controlled from an external source. This is typically done by holding one input high while applying a PWM pulse
train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching frequency. See
Typical Switching Waveforms, Figures 11 through 18, pp. 15–16.
24. The Maximum Switching Frequency during active current limiting is internally implemented. The internal current limit circuitry produces a
constant-OFF-time pulse-width modulation of the output current. The output load’s inductance, capacitance, and resistance characteristics
affect the total switching period (OFF-time + ON-time) and thus the PWM frequency during current limit.
25. Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition
direction) of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from the midpoint of the input signal to the
90% point of the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from the midpoint of the input signal to the
10% point of the output response signal. See Figure 2, page 11.
26. ILIM Output Constant-OFF Time is the time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the
output bridge.
27. Load currents ramping up to the current regulation threshold become limited at the ILIM value. The short circuit currents possess a di/dt that
ramps up to the ISCH or ISCL threshold during the ILIM blanking time, registering as a short circuit event detection and causing the shutdown
circuitry to force the output into an immediate tri-state latch-OFF. See Figures 6 and 7, page 12. Operation in Current Limit mode may cause
junction temperatures to rise. Junction temperatures above ~160°C will cause the output current limit threshold to progressively “fold back”,
or decrease with temperature, until ~175°C is reached, after which the TLIM thermal latch-OFF will occur. Permissible operation within this
foldback region is limited to nonrepetitive transient events of duration not to exceed 30 seconds. See Figure 5, page 11.
28. ILIM Blanking Time is the time during which the current regulation threshold is ignored so that the short-circuit detection threshold
comparators my have time to act.
29. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 4, page 11.
30. Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See Figure 3,
page 11.
31. Parameter has been characterized but not production tested.
32. Parameter is guaranteed by design but not production tested.
33887
10
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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