LHF16KA7 데이터 시트보기 (PDF) - Sharp Electronics

부품명

상세내역

제조사

LHF16KA7

Flash Memory 16M (2MB × 8/1MB × 16)

Sharp Electronics 

SHARP

LHFlGKA7

7

-

2.1 Data Protection

-l

3.2 Output Disable

Depending on the application, the system designer

may choose to make the V,, power supply

switchable (available only when block erase, full chip

erase, (multi) word/byte write and block lock-bit

configuration are required) or hardwired to VPPH1,2/3.

The device accommodates either design practice and

encourages optimization of the processor-memory

interface.

When Vpp~VppLKtmemory contents cannot be

altered. The CUI, with multi-step block erase, full chip

erase, (multi) word/byte write and block lock-bit

configuration command sequences, provides

protection from unwanted operations even when high

voltage,is applied to V,,. All write functions are

disabled when Vcc is below the write lockout voltage

V,,, or when RP# is at V,,. The device’s block

locking capability provides additional protection from

inadvertent code or data alteration by gating block

erase, full chip erase and (multi) word/byte write

operations.

3 BUS OPERATION

The local CPU reads and writes flash memory in-

system. All bus cycles to or from the flash memory

conform to standard microprocessor bus cycles.

3.1 Read

Information can be read from any block, identifier

codes, query structure,‘or status register independent

of the V,, voltage. RP# must be at VI,.

The first task is to write the appropriate read mode

command (Read Array, Read Identifier Codes, Query

or Read Status Register) to the CUI. Upon initial

device power-up or after exit from deep power-down

mode, the device automatically resets to read array

mode. Five control pins dictate the data flow in and

out of the component: CE# (CE,#, CE,#), OE#, WE#,

RP# and WP#. CE,#, CE,# and OE# must be driven

active to obtain data at the outputs. CE,#, CE,# is

the device selection control, and when active enables

the selected memory device. OE# is the data output

(DC&-DQ,,) control and when active drives the

selected memory data onto the I/O bus. WE# and

RP# must be at V,,. Figure 17, 18 illustrates a read

cycle.

With OE# at a logic-high level (VI,), the devict

outputs are disabled. Output pins DO,-DQ,, an

placed in a high-impedance state.

3.3 Standby

Either CE,# or CE,# at a logic-high level (V,,) place:

the device in standby mode which substantiall!

reduces device power consumption. DQo-DQ,,

outputs are placed in a high-impedance statt

independent of OE#. If deselected during bloc1

erase, full chip erase, (multi) word/byte write ant

block lock-bit configuration, the device continue:

functioning, and consuming active power until the

operation completes.

3.4 Deep Power-Down

RP# at V,, initiates the deep power-down mode.

In read modes, RP#-low deselects the memory

places output drivers in a high-impedance state ant

turns off all internal circuits. RP# must be held low fol

a minimum of 100 ns. Time t,,crv is required after

return from power-down until initial memory access

outputs are valid. After this wakeup interval, norma

operation is restored. The CUI is reset to read arra)

mode and status register is set to 80H.

During block erase, full chip erase, (multi) word/byte

write or block lock-bit configuration modes, RP#-low

will abort the operation. STS remains low until the

reset operation is complete. Memory contents being

altered are no longer valid; the data may be partially

erased or written. Time tPHWL is required after RP#

goes to logic-high (V,,) before another command can

be written.

As with any automated device, it is important tc

assert RP# during system reset. When the system

comes out of reset, it expects to read from the flash

memory. Automated flash memories provide status

information when accessed during block erase, full

chip erase, (multi) word/byte write and block lock-bit

configuration. If a CPU reset occurs with no flash

memory reset, proper CPU initialization may not

occur because the flash memory may be providing

status information instead of array data. SHARP’s

flash memories allow proper CPU initialization

following a system reset through the use of the RP#

input. In this application, RP# is controlled by the

same RESET# signal that resets the system CPU.

Rev. 1.Q

Share Link: