ICL7662 데이터 시트보기 (PDF) - Renesas Electronics
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ICL7662 Datasheet PDF : 11 Pages
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ICL7662
10F
+
-
1
8
2 ICL7662 7
3
“1”
6
4
5
V+
1
8
+
10F -
2 ICL7662 7
3
“N”
6
4
5
-
+10F
-
+10F
VOUT
FIGURE 19. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE
Changing the ICL7662 Oscillator Frequency
It may be desirable in some applications, due to noise or other
considerations, to increase the oscillator frequency. This is
achieved by overdriving the oscillator from an external clock, as
shown in Figure 20. In order to prevent possible device latchup, a
1k resistor must be used in series with the clock output. In the
situation where the designer has generated the external clock
frequency using TTL logic, the addition of a 10k pullup resistor
to V+ supply is required. Note that the pump frequency with
external clocking, as with internal clocking, will be 1/2 of the clock
frequency. Output transitions occur on the positive-going edge of
the clock.
V+
V+
+
10F-
1
8
1k
2
ICL7662
7
3
6
CMOS
GATE
4
5
-
VOUT
+ 10F
FIGURE 20. EXTERNAL CLOCKING
It is also possible to increase the conversion efficiency of the
ICL7662 at low load levels by lowering the oscillator frequency.
This reduces the switching losses, and is achieved by connecting
an additional capacitor, COSC, as shown in Figure 21. However,
lowering the oscillator frequency will cause an undesirable
increase in the impedance of the pump (C1) and reservoir (C2)
capacitors; this is overcome by increasing the values of C1 and
C2 by the same factor that the frequency has been reduced. For
example, the addition of a 100pF capacitor between pin 7 (OSC)
and V+ will lower the oscillator frequency to 1kHz from its nominal
frequency of 10kHz (a multiple of 10), and thereby necessitate a
corresponding increase in the value of C1 and C2 (from 10mF to
100mF).
V+
C1 +
-
1
8
2
ICL7662
7
3
6
COSC
4
5
-
VOUT
+ C2
FIGURE 21. LOWERING OSCILLATOR FREQUENCY
Positive Voltage Doubling
The ICL7662 may be employed to achieve positive voltage
doubling using the circuit shown in Figure 22. In this
application, the pump inverter switches of the ICL7662 are
used to charge C1 to a voltage level of V+ -VF (where V+ is the
supply voltage and VF is the forward voltage drop of diode D1).
On the transfer cycle, the voltage on C1 plus the supply voltage
(V+) is applied through diode C2 to capacitor C2. The voltage
thus created on C2 becomes (2V+) (2VF) or twice the supply
voltage minus the combined forward voltage drops of diodes
D1 and D2.
The source impedance of the output (VOUT) will depend on the
output current, but for V+ = 15V and an output current of 10mA
it will be approximately 70.
1
8
2
ICL7662
7
3
6
4
5
V+
D1
D2
+
- C1
VOUT =
(2V+) - (2VF)
+
- C2
NOTE: D1 and D2 can be any suitable diode.
FIGURE 22. POSITIVE VOLTAGE DOUBLER
FN3181 Rev.4.00
Jan 9, 2006
Page 9 of 11
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