74VHC573SJ(2007) 데이터 시트보기 (PDF) - Fairchild Semiconductor

부품명

상세내역

제조사

74VHC573SJ
(Rev.:2007)

Octal D-Type Latch with 3-STATE Outputs

Fairchild Semiconductor 

Logic Symbol

IEEE/IEC

Functional Description

The VHC573 contains eight D-type latches with

3-STATE output buffers. When the Latch Enable (LE)

input is HIGH, data on the Dn inputs enters the latches.

In this condition the latches are transparent, i.e., a latch

output will change state each time its D input changes.

When LE is LOW the latches store the information that

was present on the D inputs, a setup time preceding the

HIGH-to-LOW transition of LE. The 3-STATE buffers are

controlled by the Output Enable (OE) input. When OE is

LOW, the buffers are enabled. When OE is HIGH the

buffers are in the high impedance mode, but, this does

not interfere with entering new data into the latches.

Truth Table

Inputs

OE

LE

D

L

H

H

L

H

L

L

L

X

H

X

X

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

Logic Diagram

Outputs

On

H

L

O0

Z

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

©1993 Fairchild Semiconductor Corporation

74VHC573 Rev. 1.3

2

www.fairchildsemi.com

Share Link: