CDP68HC68T1 데이터 시트보기 (PDF) - Renesas Electronics
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CDP68HC68T1 Datasheet PDF : 24 Pages
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CDP68HC68T1
Absolute Maximum Ratings
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . VSS -0.3V to VDD +0.3V
Current Drain Per Input Pin (Excluding VDD and VSS I) . . . . . 10mA
Current Drain Per Output Pin I. . . . . . . . . . . . . . . . . . . . . . . . . 40mA
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0V to +6.0V
Standby (Timekeeping) Voltage . . . . . . . . . . . . . . . . . +2.2V to +6.0V
Temperature Range
CDP68HC68T1E (PDIP Package) . . . . . . . . . . . . .-40°C to +85°C
CDP68HC68T1M/M2 (SOIC Packages) . . . . . . . .-40°C to +85°C
Input Voltage
Input High . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(0.7 x VDD) to VDD
Input Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to (0.3 x VDD)
Serial Clock Frequency (fSCK). . . . . . . . . . . . . . . . . . +3.0V to +6.0V
Thermal Information
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
16 Ld PDIP* (Notes 1, 3) . . . . . . . . . . .
85
35
16 Ld SOIC (Notes 2, 3). . . . . . . . . . . .
65
26
20 Ld SOIC (Notes 2, 3). . . . . . . . . . . .
60
26
Maximum Junction Temperature (Plastic) . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range (TSTG). . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3. For JC, the “case temp” location is taken at the package top center.
Static Electrical Specifications At TA = -40°C to +85°C, VDD = VBATT = 5V ±5%, Unless Otherwise Specified.
CDP68HC68T1
PARAMETER
SYMBOL
TEST CONDITIONS
TYP
MIN
(Note 4)
Quiescent Device Current
Output Voltage High Level
Output Voltage Low Level
Output Voltage High Level
Output Voltage Low Level
Input Leakage Current
Three-State Output Leakage Current
Operating Current (Note 5)
(ID + IB) VDD = VB = 5V
Crystal Operation
IDD
-
VOH IOH = -1.6mA, VDD = 4.5V
3.7
VOL IOL = 1.6mA, VDD = 4.5V
-
VOH IOH 10µA, VDD = 4.5V
4.4
VOL IOL 10µA, VDD = 4.5V
-
IIN
-
IOUT
-
32kHz
-
1MHz
-
2MHz
-
1
-
-
-
-
-
-
0.08
0.5
0.7
4MHz
-
1
XTAL IN Clock (Squarewave) (Note 5)
(ID + IB) VDD = VS = 5V
32kHz
1MHz
-
0.02
-
0.1
2MHz
-
0.2
4MHz
-
0.4
Standby Current (Note 5)
VS = 3V
Crystal Operation
IB
32kHz
1MHz
2MHz
-
20
-
200
-
300
4MHz
-
500
MAX
10
-
0.4
-
0.1
±1
±10
-
-
-
-
0.024
0.12
0.24
0.5
-
-
-
-
UNITS
µA
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
FN1547 Rev 9.00
Decemember 8, 2015
Page 3 of 24
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