HI5714 데이터 시트보기 (PDF) - Renesas Electronics
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HI5714 Datasheet PDF : 14 Pages
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HI5714
Electrical Specifications VCCA = VCCD = VCCO = +5V; VRB = 1.3V; VRT = 3.6V; TA = 25oC, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
DIGITAL OUTPUTS (D0 to D7 and O/UF Referenced to OGND)
Logic Output Voltage Low, VOL
IO = 1mA
Logic Output Voltage High, VOH
IO = -0.4mA
Output Leakage Current, ID
0.4V < VOUT < VCCO
SWITCHING CHARACTERISTICS (Notes 4, 5) See Figure 1
0
-
0.4
V
2.7
-
VCCO
V
-20
-
+20
A
Sample Rate, fCLK
HI5714/7
75
-
-
MHz
HI5714/4
40
-
-
MHz
Clock Pulse Width High, tCPH
Clock Pulse Width Low, tCPL
ANALOG SIGNAL PROCESSING (fCLK = 40MHz)
Differential Gain, DG
(Notes 6, 9)
6
-
-
ns
6
-
-
ns
-
1.0
-
%
Differential Phase, DP
HARMONICS (fCLK = 75MHz)
Second Harmonic, H2
Third Harmonic, H3
Total Harmonic Distortion, THD
Spurious Free Dynamic Range, SFDR
Analog Input Bandwidth (-3dB)
TRANSFER FUNCTION
(Notes 6, 9)
fIN = 4.43MHz
fIN = 4.43MHz
fIN = 4.43MHz
fIN = 4.43MHz
-
0.05
-
degree
-
-63
-
dB
-
-65
-
dB
-
-59
-
dB
-
62
-
dB
-
18
-
MHz
Differential Linearity Error, DNL
(Note 7)
-
0.4
-
LSB
Integral Linearity Error, INL
EFFECTIVE NUMBER OF BITS
(Note 7)
-
0.75
-
LSB
ENOB
HI5714/4 (fCLK = 40MHz)
HI5714/7 (fCLK = 75MHz)
Bit Error Rate, BER
TIMING (fCLK = 75MHz) See Figures 1, 2
Sampling Delay, tSD
Output Hold Time, tHD
Output Delay Time, tD
Output Enable Delay, tPZH
Output Enable Delay, tPZL
Output Disable Delay, tPHZ
Output Disable Delay, tPLZ
Aperture Jitter, tAJ
fIN = 4.43MHz
fIN = 7.5MHz
fIN = 4.43MHz
fIN = 7.5MHz
fIN = 10MHz
(Note 8)
HI5714/4/7
Enable to High
Enable to Low
Disable from High
Disable from Low
-
7.65
-
Bits
-
7.5
-
Bits
-
7.4
-
Bits
-
7.15
-
Bits
-
6.8
-
Bits
-
10-11
-
Times/
Sample
-
-
2
ns
5
-
-
ns
-
10
13
ns
-
14.6
-
ns
-
17.8
-
ns
-
5.3
-
ns
-
6.7
-
ns
-
50
-
ps
FN3973 Rev 6.00
July 2004
Page 4 of 14
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