M48Z128(2003) 데이터 시트보기 (PDF) - STMicroelectronics

부품명

상세내역

제조사

M48Z128
(Rev.:2003)

5.0V OR 3.3V, 1 Mbit (128 Kbit x 8) ZEROPOWER® SRAM

STMicroelectronics 

M48Z128, M48Z128Y, M48Z128V*

READ Mode

The M48Z128/Y/V is in the READ Mode whenever

W (WRITE Enable) is high and E (Chip Enable) is

low. The device architecture allows ripple-through

access of data from eight of 1,048,576 locations in

the static storage array. Thus, the unique address

specified by the 17 address inputs defines which

one of the 131,072 bytes of data is to be accessed.

Valid data will be available at the Data I/O pins

within Address Access time (tAVQV) after the last

address input signal is stable, providing that the E

and G (Output Enable) access times are also sat-

isfied. If the E and G access times are not met, val-

id data will be available after the later of Chip

Enable Access time (tELQV) or Output Enable Ac-

cess Time (tGLQV). The state of the eight three-

state Data I/O signals is controlled by E and G. If

the outputs are activated before tAVQV, the data

lines will be driven to an indeterminate state until

tAVQV. If the address inputs are changed while E

and G remain low, output data will remain valid for

Output Data Hold time (tAXQX) but will go indeter-

minate until the next Address Access.

Figure 7. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms

A0-A16

E

G

DQ0-DQ7

tAVAV

VALID

tAVQV

tELQV

tELQX

tGLQV

tGLQX

tAXQX

tEHQZ

tGHQZ

DATA OUT

Note: WRITE Enable (W) = High.

Figure 8. Address Controlled, READ Mode AC Waveforms

tAVAV

A0-A16

VALID

tAVQV

AI01197

tAXQX

DQ0-DQ7

DATA VALID

Note: Chip Enable (E) and Output Enable (G) = Low, WRITE Enable (W) = High.

AI01078

9/21

Share Link: