Complete VGA 1:2 or 2:1 Multiplexer
MAX4885
V+
V+
VN_
R1, G1, B1 R0, G0, B0
R2, G2, B2
RL
SEL
LOGIC
GND
INPUT
VOUT
CL
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
( ) VOUT = VN_
RL
RL + RON
Figure 1. Switching Time
50%
INPUT
tPLH
50%
OUTPUT
tSKEW = | tPLH - tPHL |
tPD = MAX (tPLH, tPHL)
Figure 2. Propagation Delay and Skew Waveforms
Timing Circuits/Timing Diagrams
V+
LOGIC
INPUT 0V
50%
tr < 5ns
tf < 5ns
50%
SWITCH 0V
OUTPUT
tOFF
VOUT 0.9 x V0UT
0.9 x VOUT
tON
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
1V
50%
RS = RL = 50Ω
CL = 10pF
0V
tPHL
VOH
0.9V
50%
0V
MAX4885
V+
V+
VGEN
RGEN R1, G1, B1
R2, G2, B2
R0, G0, B0
GND
SEL
VIL TO VIH
Figure 3. Charge Injection
VOUT
CL
VOUT
IN
OFF
∆VOUT
OFF
ON
ON
OFF
OFF
IN
Q = (∆VOUT)(CL)
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
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