AD9816 데이터 시트보기 (PDF) - Analog Devices
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AD9816 Datasheet PDF : 16 Pages
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DIGITAL SPECIFICATIONS (TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, DRVDD = +5.0 V, fADCCLK = 6 MHz,
fCDSCLK1 = 2 MHz, fCDSCLK2 = 2 MHz, CL = 10 pF unless otherwise noted)
AD9816
Parameter
Symbol
Min
Typ
Max
Units
LOGIC INPUTS
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
High Level Input Current
IIH
Low Level Input Current
IIL
Input Capacitance
CIN
LOGIC OUTPUTS
High Level Output Voltage
VOH
Low Level Output Voltage
VOL
High Level Output Current
IOH
Low Level Output Current
IOL
Specifications subject to change without notice.
3.5
V
1.0
V
10
µA
10
µA
10
pF
4.5
V
0.1
V
50
µA
50
µA
TIMING SPECIFICATIONS (TMIN to TMAX with DVDD = +5.0 V, DRVDD = +5.0 V)
Parameter
Symbol
Min
Typ
Max
CLOCK PARAMETERS
3-Channel Conversion Rate
1-Channel Conversion Rate
ADCCLK Pulsewidth
CDSCLK1 Pulsewidth
CDSCLK2 Pulsewidth
CDSCLK1 Falling to CDSCLK2 Rising
ADCCLK Falling to CDSCLK2 Rising
CDSCLK2 Falling to ADCCLK Falling
CDSCLK2 Falling to CDSCLK1 Rising
Aperture Delay for CDS Clocks
SERIAL INTERFACE
Maximum SCLK Frequency
SLOAD to SCLK Set-Up Time
SCLK to SLOAD Hold Time
SDATA to SCLK Rising Set-Up Time
SCLK Rising to SDATA Hold Time
SCLK Falling to SDATA Valid
DATA OUTPUT
Output Delay
3-State to Data Valid
Output Enable High to 3-State
Latency (Pipeline Delay)
tCRA
tCRB
tADCLK
tC1
tC2
tC1C2
tADC2
tC2AD
tC2C1
tAD
fSCLK
tLS
tLH
tDS
tDH
tRDV
tOD
tDV
tHZ
500
160
80
20
60
2 tADCLK – 30
5
0
30
10
10
10
10
10
10
10
10
13
15
5
3 (Fixed)
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ADCCLK Cycles
REV. A
–3–
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