MC10E1651L 데이터 시트보기 (PDF) - Motorola => Freescale

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MC10E1651L

Dual ECL Output Comparator With Latch

Motorola => Freescale 

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Dual ECL Output Comparator

With Latch

The MC10E1651 is functionally and pin-for-pin compatible with the

MC1651 in the MECL III family, but is fabricated using Motorola’s

advanced MOSAIC III process. The MC10E1651 incorporates a fixed

level of input hysteresis as well as output compatibility with 10KH logic

devices. In addition, a latch is available allowing a sample and hold

function to be performed. The device is available in both a 16-pin DIP and

a 20-pin surface mount package.

The latch enable (LENa and LENb) input pins operate from standard

ECL 10KH logic levels. When the latch enable is at a logic high level the

MC10E1651 acts as a comparator, hence Q will be at a logic high level if

V1 > V2 (V1 is more positive than V2). Q is the complement of Q. When

the latch enable input goes to a low logic level, the outputs are latched in

their present state providing the latch enable setup and hold time

constraints are met.

• Typ. 3.0 dB Bandwidth > 1.0 GHz

• Typ. V to Q Propagation Delay of 775 ps

• Typ. Output Rise/Fall of 350 ps

• Common Mode Range –2.0 V to +3.0 V

• Individual Latch Enables

• Differential Outputs

• 28mV Input Hysteresis

LOGIC DIAGRAM

V1a

Qa

V2a

LENa

Qa

MC10E1651

DUAL ECL OUTPUT

COMPARATOR

WITH LATCH

FN SUFFIX

PLASTIC PACKAGE

CASE 775-02

L SUFFIX

CERAMIC PACKAGE

CASE 620-10

FUNCTION TABLE

LEN

H

H

L

V1, V2

V1 > V2

V1 < V2

X

Function

H

L

Latched

V1b

V2b

LENb

Qb

Qb

VEE = –5.2 V

VCC = +5.0 V

12/93

© Motorola, Inc. 1996

2–1

REV 1

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