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MC100E156FNR2

5V
ECL 3-Bit 4:1 Mux-Latch

ON Semiconductor 

MC10E156, MC100E156

5V ECL 3-Bit 4:1 Mux-Latch

The MC10E/100E156 contains three 4:1 multiplexers followed by

transparent latches with differential outputs. When both Latch Enables

(LEN1, LEN2) are LOW, the latch is transparent, and output date is

controlled by the multiplexer select controls (SEL0, SEL1). A logic

HIGH on either LEN1 or LEN2 (or both) latches the outputs. The

Master Reset (MR) overrides all other controls to set the Q outputs

LOW.

The 100 Series contains temperature compensation.

• 950 ps Max. D to Output

• 850 ps Max. LEN to Output

• Differential Outputs

• Asynchronous Master Reset

• Dual Latch-Enables

• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V

with VEE = 0 V

• NECL Mode Operating Range: VCC= 0 V

with VEE = −4.2 V to −5.7 V

• Internal Input 50 KW Pulldown Resistors

• ESD Protection: Human Body Model; > 2 KV,

Machine Model; > 200 V

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

• Moisture Sensitivity Level 1

For Additional Information, see Application Note AND8003/D

• Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

• Transistor Count = 271 devices

http://onsemi.com

MARKING

DIAGRAMS

1 28

PLCC−28

FN SUFFIX

CASE 776

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

MC10E156FN

AWLYYWW

1 28

MC100E156FN

AWLYYWW

ORDERING INFORMATION

Device

Package

Shipping†

MC10E156FN

PLCC−28 37 Units/Rail

MC10E156FNR2

MC100E156FN

PLCC−28

PLCC−28

500 Units/Reel

37 Units/Rail

MC100E156FNR2 PLCC−28 500 Units/Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

© Semiconductor Components Industries, LLC, 2003

1

December, 2003 − Rev. 6

Publication Order Number:

MC10E156/D

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