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MC14008B

4−Bit Full Adder

ON Semiconductor 

MC14008B

4−Bit Full Adder

The MC14008B 4−bit full adder is constructed with MOS

P−Channel and N−Channel enhancement mode devices in a single

monolithic structure. This device consists of four full adders with fast

internal look−ahead carry output. It is useful in binary addition and

other arithmetic applications. The fast parallel carry output bit allows

high−speed operation when used with other adders in a system.

Features

• Look−Ahead Carry Output

• Diode Protection on All Inputs

• All Outputs Buffered

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low−Power TTL Loads or One

Low−Power Schottky TTL Load Over the Rated Temperature Range

• Pin−for−Pin Replacement for CD4008B

• Pb−Free Packages are Available*

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol

Parameter

Value

Unit

VDD

Vin, Vout

DC Supply Voltage Range

Input or Output Voltage Range

(DC or Transient)

−0.5 to +18.0

V

−0.5 to VDD + 0.5

V

Iin, Iout

Input or Output Current

(DC or Transient) per Pin

± 10

mA

PD

Power Dissipation, per Package

500

mW

(Note 1)

TA

Ambient Temperature Range

−55 to +125

°C

Tstg

Storage Temperature Range

−65 to +150

°C

TL

Lead Temperature

(8−Second Soldering)

260

°C

Maximum ratings are those values beyond which device damage can occur.

Maximum ratings applied to the device are individual stress limit values (not

normal operating conditions) and are not valid simultaneously. If these limits are

exceeded, device functional operation is not implied, damage may occur and

reliability may be affected.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

http://onsemi.com

MARKING

DIAGRAMS

PDIP−16 16

P SUFFIX

CASE 648

1

MC14008BCP

AWLYYWWG

SOIC−16

D SUFFIX

CASE 751B

16

14008BG

AWLYWW

1

A

WL, L

YY, Y

WW, W

G

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Indicator

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2005

1

August, 2005 − Rev. 6

Publication Order Number:

MC14008B/D

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