74LVC00APW 데이터 시트보기 (PDF) - NXP Semiconductors.
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74LVC00APW Datasheet PDF : 14 Pages
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4. Functional diagram
74LVC00A
Quad 2-input NAND gate
1 1A
2 1B
4 2A
5 2B
9 3A
10 3B
12 4A
13 4B
1Y 3
2Y 6
3Y 8
4Y 11
mna212
Fig 1. Logic symbol
1
2
&
3
4
5
&
6
9
10
&
8
12
13
&
11
mna246
Fig 2. IEC logic symbol
5. Pinning information
5.1 Pinning
A
Y
B
mna211
Fig 3. Logic diagram for one gate
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 VCC
13 4B
12 4A
00
11 4Y
10 3B
9 3A
8 3Y
001aac938
Fig 4. Pin configuration SO14 and (T)SSOP14
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
VCC
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8,11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
terminal 1
index area
1B 2
1Y 3
2A 4
2B 5
2Y 6
00
GND (1)
13 4B
12 4A
11 4Y
10 3B
9 3A
001aac939
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration DHVQFN14
74LVC00A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 25 April 2012
© Nexperia B.V. 2017. All rights reserved
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