AM29LV004 데이터 시트보기 (PDF) - Advanced Micro Devices

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AM29LV004

4 Megabit (512 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory

Advanced Micro Devices 

PRELIMINARY

Standby Mode

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at VCC ± 0.3 V.

(Note that this is a more restricted voltage range than

VIH.) If CE# and RESET# are held at VIH, but not within

VCC ± 0.3 V, the device will be in the standby mode, but

the standby current will be greater. The device requires

standard access time (tCE) for read access when the

device is in either of these standby modes, before it is

ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

In the DC Characteristics tables, ICC3 and ICC4 repre-

sents the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device

energy consumption. The device automatically

enables this mode when addresses remain stable for

tACC + 30 ns. The automatic sleep mode is indepen-

dent of the CE#, WE#, and OE# control signals. Stan-

dard address access timings provide new data when

addresses are changed. While in sleep mode, output

data is latched and always available to the system. ICC5

in the DC Characteristics table represents the auto-

matic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of reset-

ting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of tRP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is ready

to accept another command sequence, to ensure data

integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VSS±0.3 V, the device

draws CMOS standby current (ICC4). If RESET# is held

at VIL but not within VSS±0.3 V, the standby current will

be greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The

system can thus monitor RY/BY# to determine

whether the reset operation is complete. If RESET# is

asserted when a program or erase operation is not ex-

ecuting (RY/BY# pin is “1”), the reset operation is

completed within a time of tREADY (not during Embed-

ded Algorithms). The system can read data tRH after

the RESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 13 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is

disabled. The output pins are placed in the high imped-

ance state.

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Am29LV004

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