LC8902 데이터 시트보기 (PDF) - SANYO -> Panasonic

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LC8902

Digital Audio Interface Receiver

SANYO -> Panasonic 

LC8902, 8902Q

The LC8902/Q uses the subcode synchronization word and the start bit in the user bits for subcode interface system

timing extraction. Therefore, SBSY and SFSY change depending on that timing. Keep the following notes on user bit

transfer in mind when using the values of tBW, tF, tCHW and tCD within the specifications described above. Basically,

user bit transfers must follow the table shown here.

Note: 7. Subcode synchronization is taken as a block synchronization section (the start of a block) when a minimum of 22 consecutive data bits are zero.

8. The frame sync signal S0 period is 90.7 µs. The S1 period also has a minimum value of 90.7 µs (when there are 22 consecutive zero data bits),

depending on the subcode sync word period.

9. When the shortest user data word length is used, the SBCK signal delay (tHD) and pulse widths (tCHW and tCLW) must be set at or below their

typical values.

No. 4333-5/14

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