NT6880H 데이터 시트보기 (PDF) - Novatek Microelectronics
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NT6880H Datasheet PDF : 13 Pages
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Block Diagram
Timing Generator
(RC OSC/Ceramic Resonator: 4MHz)
5K Bytes
ROM
RESET
VDD
GND
6502
CPU
Interrupt
Controller
Power-On RESET/
Low Voltage RESET
160 Bytes
SRAM + STACK
Watch Dog
Timer
Base Timer
NT6880
I/O PORTs
CLK
DATA
LED0
LED1
LED2
P00 - P07
P10 - P17
P20 - P27
P30 - P34
Pin and Pad Descriptions
Pin No. Pad No. Designation I/O
1
1
GND
P
2
2
NC
-
3
3
DATA
I/O
4
4
CLK
I/O
5 - 9,
5 - 9,
P30 - P34,
I/O
11 - 34 11 - 34 P00 - P27
10
10
RESET
I
35 - 37 35 - 37
LED0 -
O
LED2
38
38
VDD
P
39
39
R/OSCO
I
40
40
OSCI
-
Description
Ground pin
No connection, recommended to connect VDD or floating
I/O, 10KΩ pull-up resistor for communication
I/O, 10KΩ pull-up resistor for communication
Bi-directional I/O pins
RESET signal input pin with internal pull up resistor; Active low
LED direct sink pins
Power supply
47KΩ resistor connected for RC OSC or 4MHz ceramic resonator
connected
No connection for RC OSC connected for 4MHz ceramic resonator
* Under the constraint of the maximum frequency variation, (∆F/F)max, ≤ ±1%, code 3, 7 (ceramic resonator option) must
be selected and pin 39 and pin 40 must be connected to a ceramic resonator. If (∆F/F)max, ≤ ±10%, code 1, 5 (RC OSC
option) it is recommended that pin 39 be connected to a 47KΩ resistor with ≤ ±1% accuracy to VDD. Pin 40 is floating.
2
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