STK681-352-E 데이터 시트보기 (PDF) - ON Semiconductor
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STK681-352-E Datasheet PDF : 14 Pages
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Sample Application Circuit
STK681-352-E
STK681-352-E
FAULT
3.3V
IN1
IN2
ENABLE
(DC or PWM)
C2
10F/50V
13
N.C 15
16
17
18
R1
Vref
19
R2
C3
0.1F
14
S.GND
9
VCC=24V
7
10
OUT1
8
12
N.C
11
N.C
OUT2
6
Motor
5
N.C
4
3
C1
47F to /50V
2
Rs
1
CCW
CW
GND
Motor Drive Conditions (H: High-level input; L: Low-Level Input)
Stop
IN1
IN2
ENABLE
Remarks
H
L
L
Turns the power supply OFF.
L
H
L
ENABLE must be set Low when VCC is rising or falling.
H
H
L
Forward (CW)
Reverse (CCW)
H
L
H
No input signal is needed that turns off the upper- and
lower-side drive devices when switching the rotational
L
H
H
direction.
Brake
L
L
L or H
VCC side Brake MOSFET ON
H
H
H
GND side Brake MOSFET ON
* Output control is enabled by applying an external PWM signal to the ENABLE pin.
The product can run at a minimum external PWM pulse width of 1s. In the case when the high pulse width is less
than 16s, however, the IC may fail to detect a short-circuit condition when an output short-circuit occurs.
FAULT signal is generated to indicate an error condition if VCC falls below the allowable operating range when the
ENABLE pin is set to high during motor rotation or PWM operation. For this reason, ENABLE must be set to low
when VCC is rising or falling.
When both IN1 and IN2 are set low, the MOSFET on the VCC side is driven. To minimize the loss when stopped, set
IN1 = IN2 = High and ENABLE = Low to turn off the gate signal to the VCC side MOSFETs.
Setting the current limit using the Vref pin
Peak output current (Iop) = (Vref ÷ 4.9) ÷ Rs
“4.9” in the above formula indicates the portion of the Vref voltage that is divided using the circuit inside the
control IC.
Vref = (R2 ÷ (R1 + R2)) × 5.0V
Rs is the external current detection resistance value of the HIC, and Vref 2.0V must be satisfied so that
overcurrent detection is not triggered.
No.A1929-6/14
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