HEC4040BT-T 데이터 시트보기 (PDF) - NXP Semiconductors.
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HEC4040BT-T Datasheet PDF : 14 Pages
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HEF4040B
12-stage binary ripple counter
Rev. 8 — 17 November 2011
Product data sheet
1. General description
The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The
counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter
stages and forces all outputs LOW, independent of CP. Each counter stage is a static
toggle flip-flop. The clock input is highly tolerant of slow rise and fall times due to its
Schmitt trigger action.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Tolerant of slow clock rise and fall time
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
Frequency dividing circuits
Time delay circuits
Control counters
4. Ordering information
Table 1. Ordering information
All types operate from 40 C to +85 C.
Type number Package
Name
Description
HEF4040BP
DIP16
plastic dual in-line package; 16 leads (300 mil)
HEF4040BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT38-4
SOT109-1
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