74HC4515(2018) 데이터 시트보기 (PDF) - NXP Semiconductors.

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74HC4515
(Rev.:2018)

4-to-16 line decoder/demultiplexer with input latches; inverting

NXP Semiconductors. 

Nexperia

74HC4515

4-to-16 line decoder/demultiplexer with input latches; inverting

Symbol Parameter

Conditions

Tamb (°C)

Unit

+25

−40 to +85 −40 to +125

Min Typ Max Min Max Min Max

tsu

set-up time

An to LE; see Figure 7

VCC = 2.0 V

90 28

- 115 - 135 - ns

VCC = 4.5 V

18 10

-

23

-

27

- ns

th

hold time

VCC = 6.0 V

An to LE; see Figure 7

VCC = 2.0 V

15 8

-

20

-

23

- ns

0 −11 -

0

-

0

- ns

VCC = 4.5 V

0

−4

-

0

-

0

- ns

VCC = 6.0 V

0

−3

-

0

-

0

- ns

CPD

power dissipation per package; VI = GND to VCC [3] -

44

-

-

-

-

- pF

capacitance

[1] tpd is the same as tPLH and tPHL

[2] tt is the same as tTLH and tTHL

[3] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD x VCC2 x fi x N + Σ(CL x VCC2 x fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of load switching outputs;

Σ(CL x VCC2 x fo) = sum of the outputs.

11.1 Waveforms and test circuit

VI

LE input

VM

VM

GND

VI

An, E input

VM

VM

GND

tPHL

tPLH

VOH

Qn output

VOL

VY

VM

VX

tTHL

VY

VM

VX

tTLH

aaa-028698

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Figure 6. The inputs (An, LE, E) to output (Qn) propagation delays and the output transition times

74HC4515

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 2 July 2018

© Nexperia B.V. 2018. All rights reserved.

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