CY7C197N(2011) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C197N
(Rev.:2011)

256 K × 1 Static RAM

Cypress Semiconductor 

CY7C197N

Switching Waveforms

Figure 3. Read Cycle No. 1[10, 11]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Figure 4. Read Cycle No. 2[10]

DATA VALID

CE

DATA OUT

VCC

SUPPLY

CURRENT

ADDRESS

CE

WE

DATA IN

DATA OUT

tRC

tACE

tLZCE

HIGH IMPEDANCE

tPU

50%

DATA VALID

Figure 5. Write Cycle No. 1 (WE Controlled)[12]

tWC

tHZCE

HIGH

IMPEDANCE

tPD

ICC

50%

ISB

tSCE

tAW

tSA

DATA UNDEFINED

tHA

tPWE

tSD

tHD

DATA VALID

tHZWE

tLZWE

HIGH IMPEDANCE

C197-8

Notes

10. WE is HIGH for read cycle.

11. Device is continuously selected, CE = VIL.

12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

Document #: 001-06495 Rev. *D

Page 6 of 13

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