MT9125AE 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9125AE

Dual ADPCM Transcoder

Zarlink Semiconductor Inc 

Preliminary Information

MT9125

Mode Selection (MS1, MS2, MS3, MS4)

Separate mode select pins are available for per-

channel B1 and B2 operation. MS1 and MS2 are

used to configure the B1 channel while MS3 and

MS4 configure the B2 channel. Normally the mode

select pins are operated as static control lines. The

exception to this is for on-the-fly programming to/

from 32 kbit/s from/to 24 kbit/s modes.

B1 Channel

MS2

0

0

1

1

MS1

0

1

0

1

Operational Mode

algorithm reset

ADPCM bypass mode

(24 or 32 kbit/s)

24 kbit/s ADPCM mode

32 kbit/s ADPCM mode

B2 Channel

MS4 MS3

0

0

0

1

1

0

1

1

Algorithm Reset Mode

An algorithm reset is accomplished by forcing all

mode select pins simultaneously to logic zero. While

asserted, this will cause the device to incrementally

converge the internal variables of both channels to

the 'Optional reset values' per G.721. Invoking the

reset conditon on only one channel will cause that

channel to be reset properly and the other channel’s

operation to be undefined. This optional reset

requires that the master clock (MCLK) and frame

pulse (ENB1/2 or F0i) remain active and that the

reset condition be valid for at least four frames. Note

that this is not a power down mode.

ADPCM By-Pass Mode

In ADPCM bypass mode the B1 and B2 channel

words are transparently relayed (with a two-frame

delay) to/from the ADPCM port and placed into the

most significant nibbles of the B1 and B2 channel

PCM octets. Refer to Figure 5. The ability to transfer

ADPCM words transparently through the transcoder

enables set-to-set connections for wireless

telephony applications.

24 kbit/s Mode

In 24 kbit/s mode (CCITT G.723) PCM octets are

transcoded into three bit words rather than the four

bit words of the standard 32 kbit/s ADPCM. This is

useful in situations where lower bandwidth

transmission is required. Dynamic operation of the

mode select control pins will allow switching from 32

kbit/s mode to 24 kbit/s mode on a frame by frame

basis. Figure 6 shows the internal pipelining of the

conversion sequence and how the mode select pins

are to be used. Fig. 15 details the timing

ADPCMi

DSTo

ADPCMo

Dual ADPCM Transcoder

DSTi

B1

3210

B2

3 2 1 0 ADPCM i/o

DSTi/o 3 2 1 0 X X X X

B1

3210 XXXX

B2

In ADPCM by-pass mode, the B1 and B2 channel ADPCM

words are transparently passed (with a two frame delay) to

the most significant nibbles of the PCM octets. This feature

allows two voice terminals, which utilize ADPCM transcod-

ing, to communicate through a system (i.e., PBX, key-system)

without incurring unnecessary transcode conversions. This

arrangement also allows byte-wide or nibble-wide transport

through a switching matrix.

Figure 5 - ADPCM By-pass Mode

requirements necessary for on-the-fly control of the

Mode Select pins. The 3-bit ADPCM words occupy

the most significant bit positions of the standard 4-bit

ADPCM word.

32 kbit/s ADPCM Mode

In 32 kbit/s mode PCM octets are transcoded into

four bit words as described in CCITT G.721. This is

the standard mode of operation and, if the other

modes are not required, can be implemented by

simply tying the per-channel mode select pins to

VDD.

Master Clock (MCLK)

A 4.096 MHz master clock is required for execution

of the dual transcoding algorithm. The algorithm

requires 512 cycles of MCLK during one frame for

proper operation. This input, at the MCLK pin, may

be asynchronous with the 8 kHz frame provided that

the lowest frequency, and/or deviation due to clock

jitter, still meets the minimum strobe period

requirement of 512 tC4P -50nSec. (See AC Electrical

Characteristics - Serial PCM/ADPCM Interfaces.)

For example, a system producing large jitter values

can be accommodated by running an over-speed

MCLK to ensure that a minimum 512 MCLK cycles

per frame is obtained. The minimum MCLK period is

190 nSeconds, which translates to a maximum

frequency of 5.26 MHz. Extra MCLK cycles (>512/

frame) are acceptable because the transcoder is re-

aligned by the appropriate strobe signals each

frame.

8-79

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