DSP1627(2000) 데이터 시트보기 (PDF) - Agere -> LSI Corporation
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DSP1627 Datasheet PDF : 154 Pages
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DSP1627 Digital Signal Processor
Data Sheet
March 2000
4 Hardware Architecture (continued)
Parallel Host Interface (PHIF)
The PHIF is a passive, 8-bit parallel port which can in-
terface to an 8-bit bus containing other Lucent Technol-
ogies DSPs (e.g., DSP1620, DSP1627, DSP1628,
DSP1629, DSP1611, DSP1616, DSP1617, DSP1618),
microprocessors, or peripheral I/O devices. The PHIF
port supports either Motorola or Intel protocols, as well
as 8-bit or 16-bit transfers, configured in software. The
port data rate depends upon the instruction cycle rate.
A 25 ns instruction cycle allows the PHIF to support
data rates up to 11.85 Mbytes/s, assuming the external
host device can transfer 1 byte of data in 25 ns.
The PHIF is accessed in two basic modes: 8-bit or
16-bit mode. In 16-bit mode, the host determines an ac-
cess of the high or low byte. In 8-bit mode, only the low
byte is accessed. Software-programmable features al-
low for a glueless host interface to microprocessors
(see Section 4.8, Parallel Host Interface).
Timer
The timer can be used to provide an interrupt at the ex-
piration of a programmed interval. The interrupt may be
single or repetitive. More than nine orders of magnitude
of interval selection are provided. The timer may be
stopped and restarted at any time.
Hardware Development System (HDS) Module
The on-chip HDS performs instruction breakpointing
and branch tracing at full speed without additional off-
chip hardware. Using the JTAG port, the breakpointing
is set up, and the trace history is read back. The port
works in conjunction with the HDS code in the on-chip
ROM and the hardware and software in a remote com-
puter. The HDS code must be linked to the user's appli-
cation code and reside in the first 4 Kwords of ROM.
The on-chip HDS cannot be used with the secure ROM
masking option (see Section 7.3, ROM Security Op-
tions).
Four hardware breakpoints can be set on instruction ad-
dresses. A counter can be preset with the number of
breakpoints to receive before trapping the core. Break-
points can be set in interrupt service routines. Alternate-
ly, the counter can be preset with the number of cache
instructions to execute before trapping the core.
Every time the program branches instead of executing
the next sequential instruction, the addresses of the in-
structions executed before and after the branch are
caught in circular memory. The memory contains the
last four pairs of program discontinuities for hardware
tracing.
In systems with multiple processors, the processors
may be configured such that any processor reaching a
breakpoint will cause all the other processors to be
trapped (see Section 4.3, Interrupts and Trap).
Pin Multiplexing
In order to allow flexible device interfacing while main-
taining a low package pin count, the DSP1627 multi-
plexes 16 package pins between BIO, PHIF, VEC[3:0],
and SIO2.
Upon reset, the vectored interrupt indication signals,
VEC[3:0], are connected to the package pins while
IOBIT[4:7] are disconnected. Setting bit 12, EBIOH, of
the ioc register connects IOBIT[4:7] to the package pins
and disconnects VEC[3:0].
Upon reset, the parallel host interface (PHIF) is con-
nected to the package pins while the second serial port
(SIO2) and IOBIT[3:0] are disconnected. Setting bit 10,
ESIO2, of the ioc register connects the SIO2 and
IOBIT[3:0] and disconnects the PHIF.
Power Management
Many applications, such as portable cellular terminals,
require programmable sleep modes for power manage-
ment. There are three different control mechanisms for
achieving low-power operation: the powerc control reg-
ister, the STOP pin, and the AWAIT bit in the alf register.
The AWAIT bit in the alf register allows the processor to
go into a power-saving standby mode until an interrupt
occurs. The powerc register configures various power-
saving modes by controlling internal clocks and periph-
eral I/O units. The STOP pin controls the internal pro-
cessor clock. The various power management options
may be chosen based on power consumption and/or
wake-up latency requirements.
4.2 DSP1600 Core Architectural Overview
Figure 4 shows a block diagram of the DSP1600 core.
System Cache and Control Section (SYS)
This section of the core contains a 15-word cache mem-
ory and controls the instruction sequencing. It handles
vectored interrupts and traps, and also provides decod-
ing for registers outside of the DSP1600 core. SYS
stretches the processor cycle if wait-states are required
(wait-states are programmable for external memory ac-
cesses). SYS sequences downloading via JTAG of self-
test programs to on-chip, dual-port RAM.
The cache loop iteration count can be specified at run
time under program control as well as at assembly time.
10
Lucent Technologies Inc.
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