CXD2460R 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD2460R

Timing Generator for Progressive Scan CCD Image Sensor

Sony Semiconductor 

CXD2460R

CTGRY: System setting data

D12

SGXEN

Detailed description

0: Internal SSG (Sync Signal Generator) functions operate to generate FRO and HRO.

1: Internal SSG functions are stopped, and the FRO and HRO pulses are fixed to low.

Note that the STB setting has priority. Set SGXEN to "1" in the case of input of a CXD2460R

sync signal from the outside.

D13

EXSG

0: Normal operation

1: XSGA and XSGB are output from the HRO and FRO pins.

Note that the output pulse amplitude is VSS to VDDa.

D14

to

D15

IDSEL

These bits select the pulse output from the ID pin.

D15

0

1

0 ID pulse output WEN pulse output

D14

1 XSUB pulse output ID pulse output

XSUB: Inverted SUB pulse output at the amplitude of VSS to VDDa

D16

VTXEN

0: VT (readout clock) is added to V2A, V2B and V3 as normal.

1: VT is not added to V2A, V2B and V3.

During readout, only the modulation necessary for readout is performed.

Note that this setting has priority over mode control data NSG (D14).

D17

0: Checksum is not performed and the checksum data is invalid. (However, dummy data must be

set in the CHKSUM register.)

CHKSUM 1: Checksum is performed. This data is reflected even if the checksum results are NG.

D18

STATUS

0: The EXP pulse is output from the EXP pin.

1: High is indicated if the checksum results from the EXP pin are OK, and low if the results are NG.

This pulse is output at the rise of SEN, and reset high again at the fall of SEN. This pulse has

priority over mode control data EXP.

D19

to

Input "0".

D22

D23

to

D29

FVFS

These bits set the high-speed sweep period (unit: H) in FS mode.

MSB

LSB

D29 D28 D27 D26 D25 D24 D23

The high-speed sweep is perfomed for 8 lines for every 1H when FINE = 1, and 20 lines for every

1H when FINE = 0.

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