MC100LVEL38 데이터 시트보기 (PDF) - ON Semiconductor

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MC100LVEL38

3.3VECL ÷2, ÷4/6 Clock Generation Chip

ON Semiconductor 

MC100LVEL38

VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE

20 19 18 17 16 15 14 13 12 11

1 2 3 4 5 6 7 8 9 10

VCC EN DIV_SEL CLK CLK VBB MR VCC Phase_Out Phase_Out

Figure 1. Pinout: 20-Lead SOIC (Top View)

Warning: All VCC and VEE pins must be externally connected

to Power Supply to guarantee proper operation.

Q0

CLK

÷2

Q0

CLK

R

Q1

Q1

EN

R

MR

DIVSEL

÷4/6

R

Phase

Out

R Logic

Q2

Q2

Q3

Q3

PHASE_OUT

PHASE_OUT

VBB

Figure 2. Logic Diagram

Table 1. PIN DESCRIPTION

Table 2. FUNCTION TABLE

Pin

Function

CLK

EN

MR

Function

CLK, CLK

Q0, Q1; Q0, Q1

Q2, Q3; Q2, Q3

EN

MR

ECL Diff Clock Inputs

ECL Diff ÷2 Outputs

ECL Diff ÷4/6 Outputs

ECL Sync Enable Input

ECL Master Reset Input

Z

L

ZZ

H

X

X

Z = Low-to-High Transition

ZZ = High-to-Low Transition

X = Don’t Care

L

Divide

L

Hold Q0−3

H

Reset Q0−3

DIVSEL

Phase_Out, Phase_Out

VBB

VCC

VEE

ECL Frequency Select Input

ECL Phase Sync Diff. Signal Output

Reference Voltage Output

Positive Supply

Negative Supply

DVSEL

L

H

Q2, Q3 OUTPUTS

Divide by 4

Divide by 6

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