MC100EL38(2008) 데이터 시트보기 (PDF) - ON Semiconductor

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MC100EL38
(Rev.:2008)

5V ECL ÷2, ÷4/6 Clock Generation Chip

ON Semiconductor 

MC100EL38

5V ECL ÷2, ÷4/6 Clock

Generation Chip

The MC100EL38 is a low skew ÷2, ÷4/6 clock generation chip

designed explicitly for low skew clock generation applications. The

internal dividers are synchronous to each other, therefore, the common

output edges are all precisely aligned. The device can be driven by

either a differential or single-ended ECL or, if positive power supplies

are used, PECL input signal.

http://onsemi.com

The VBB pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

differential input is connected to VBB as a switching reference voltage.

VBB may also rebias AC coupled inputs. When used, decouple VBB

and VCC via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, VBB should be left open.

The common enable (EN) is synchronous so that the internal

dividers will only be enabled/disabled when the internal clock is

already in the LOW state. This avoids any chance of generating a runt

clock pulse on the internal clock when the device is enabled/disabled

SO−20 WB

DW SUFFIX

CASE 751D

MARKING DIAGRAM*

as can happen with an asynchronous control. An internal runt pulse

could lead to losing synchronization between the internal divider

20

stages. The internal enable flip−flop is clocked on the falling edge of

the input clock, therefore, all associated specification limits are

100EL38

referenced to the negative edge of the clock input.

AWLYYWWG

The Phase_Out output will go HIGH for one clock cycle whenever

the ÷2 and the ÷4/6 outputs are both transitioning from a LOW to a

1

HIGH. This output allows for clock synchronization within the system.

Upon startup, the internal flip-flops will attain a random state;

therefore, for systems which utilize multiple EL38s, the master reset

A

= Assembly Location

WL = Wafer Lot

(MR) input must be asserted to ensure synchronization. For systems

which only use one EL38, the MR pin need not be exercised as the

internal divider design ensures synchronization between the ÷2 and

YY

= Year

WW = Work Week

G

= Pb−Free Package

the ÷4/6 outputs of a single device.

• 50 ps Output-to-Output Skew

• Synchronous Enable/Disable

*For additional marking information, refer to

Application Note AND8002/D.

• Master Reset for Synchronization

• ESD Protection: > 2 kV Human Body Model,

> 100 V Machine Model

• The 100 Series Contains Temperature Compensation

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V

• Moisture Sensitivity Pb = Level 1

with VEE = 0 V

• NECL Mode Operating Range: VCC = 0 V with

VEE = −4.2 V to −5.7 V

• Internal 75 kW Input Pulldown Resistors on CLK, EN,

Pb−Free = Level 3

For Additional Information, see Application Note

AND8003/D

• Flammability Rating: UL 94 V−0 @ 0.125 in,

MR, and DIVSEL

• Q Output will Default LOW with Inputs Open or at

VEE

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC

Oxygen Index: 28 to 34

• Transistor Count = 388 devices

• Pb−Free Packages are Available*

Latchup Test

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2008

1

November, 2008 − Rev. 8

Publication Order Number:

MC100EL38/D

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