MF6 데이터 시트보기 (PDF) - Unspecified

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MF6

6th Order Switched Capacitor Butterworth Lowpass Filter

Unspecified 

Pin Descriptions (Pin Numbers) (Continued)

Pin

AGND (5)

VO1 (4),

INV1 (13)

VO2 (2),

INV2 (14),

NINV2 (1)

V+(6), V−(10)

CLK IN (9)

CLK R (11)

L. Sh (12)

Description

The analog ground pin. This pin sets

the DC bias level for the filter section

and the non-inverting input of

Op-Amp #1 and must be tied to the

system ground for split supply

operation or to mid-supply for single

supply operation (see section 1.2).

When tied to mid-supply this pin

should be well bypassed.

VO1 is the output and INV1 is the

inverting input of Op-Amp #1. The

non-inverting input of this Op-Amp is

internally connected to the AGND

pin.

VO2 is the output, INV2 is the

inverting input, and NINV2 is the

non-inverting input of Op-Amp #2.

The positive and negative supply

pins. The total power supply range is

5V to 14V. Decoupling these pins

with 0.1 µF capacitors is highly

recommended.

A CMOS Schmitt-trigger input to be

used with an external CMOS logic

level clock. Also used for

self-clocking Schmitt-trigger oscillator

(see section 1.1).

A TTL logic level clock input when in

split supply operation (±2.5V to

±7V) and L. Sh tied to system

ground. This pin becomes a low

impedance output when L. Sh is tied

to V−. Also used in conjunction with

the CLK IN pin for a self clocking

Schmitt-trigger oscillator (see section

1.1).

Level shift pin, selects the logic

threshold levels for the desired

clock. When tied to V− it enables an

internal tri-state® buffer stage

between the Schmitt trigger and the

internal clock level shift stage thus

enabling the CLK IN Schmitt-trigger

input and making the CLK R pin a

low impedance output.

When the voltage level at this input

exceeds [25%(V+ − V−) + V−] the

internal tri-state buffer is disabled

allowing the CLK R pin to become

the clock input for the internal clock

level shift stage. The CLK R

threshold level is now 2V above the

voltage applied to the L. Sh pin.

Driving the CLK R pin with TTL logic

levels can be accomplished through

the use of split supplies and by tying

the L. Sh pin to system ground.

9

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