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UPSD3212A(2009) 데이터 시트보기 (PDF) - STMicroelectronics

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UPSD3212A Datasheet PDF : 181 Pages
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UPSD3212A, UPSD3212C, UPSD3212CV
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UPSD321xx description
UPSD321xx description
The UPSD321xx Series combines a fast 8051-based microcontroller with a flexible memory
structure, programmable logic, and a rich peripheral mix including USB, to form an ideal
embedded controller. At its core is an industry-standard 8032 MCU operating up to 40MHz.
A JTAG serial interface is used for In-System Programming (ISP) in as little as 10 seconds,
perfect for manufacturing and lab development.
The USB 1.1 low-speed interface has one Control endpoint and two Interrupt endpoints
suitable for HID class drivers.
The 8032 core is coupled to Programmable System Device (PSD) architecture to optimize
the 8032 memory structure, offering two independent banks of Flash memory that can be
placed at virtually any address within 8032 program or data address space, and easily
paged beyond 64 Kbytes using on-chip programmable decode logic.
Dual Flash memory banks provide a robust solution for remote product updates in the field
through In-Application Programming (IAP). Dual Flash banks also support EEPROM
emulation, eliminating the need for external EEPROM chips.
General purpose programmable logic (PLD) is included to build an endless variety of glue-
logic, saving external logic devices. The PLD is configured using the software development
tool, PSDsoft Express, available from the web at www.st.com/psm, at no charge.
The UPSD321xx also includes supervisor functions such as a programmable watchdog
timer and low-voltage reset.
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
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