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NJU6631ACH 데이터 시트보기 (PDF) - Japan Radio Corporation

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NJU6631ACH
JRC
Japan Radio Corporation  JRC
NJU6631ACH Datasheet PDF : 32 Pages
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NJU6631A
(3-3) Initialization by instruction
If the power supply conditions for the correct operation of the internal reset circuits are not met, the
NJU6631A must be initialized by the instruction.
(a) Initialization by Instruction in 8-bit interface
Power On
Initialized.
No display appears.
Wait more than 15ms
after VDD rises to 4.5V
Function Set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function Set
0 0 0 0 1 1 * * * * (8-bit interface length)
Wait more than 4.1ms
Function Set
Function Set
0 0 0 0 1 1 * * * * (8-bit interface length)
Wait more than 100us
Function Set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function Set
0 0 0 0 1 1 * * * * (8-bit interface length)
Busy Flag(BF) can not be
checked before this step, but
it can be checked after this
step.
After this step, busy flag(BF)
check or longer waiting
time than each instruction
execution time is required.
Function Set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Set the 8-bit operation, 16-
0 0 0 0 1 1 1 * 0 0 Character 1-Line, Pin
Configuration mode A,
Addressing Mode 2.
Display Off
0000001000
Display Clear
0000000001
Entry Mode Set
Example for set address
increment and cursor right
0 0 0 0 0 0 0 1 1 0 shift when the data write to
the DD or CG RAM.
Write data to the DD/CG RAM and set
the Instruction

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