ISL59424 데이터 시트보기 (PDF) - Renesas Electronics
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ISL59424 Datasheet PDF : 14 Pages
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ISL59424, ISL59445
AC Test Circuits
ISL59424, ISL59445
VIN
50
OR
75
CL
1.5pF
RL
500
ISL59424, ISL59445
VIN
RS
50
OR
75
CL
1.5pF
475
OR
462.5
50
OR
75
TEST
EQUIPMENT
50
OR
75
FIGURE 18A. TEST CIRCUIT WITH OPTIMAL OUTPUT
LOAD
FIGURE 18B. TEST CIRCUIT FOR MEASURING WITH
50Ω OR 75Ω INPUT TERMINATED
EQUIPMENT
ISL59424, ISL59445
VIN
RS
50
CL 50 OR 75
OR
1.5pF
75
TEST
EQUIPMENT
50
OR
75
FIGURE 18C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. BANDWIDTH AND LINEARITY FOR RL
LESS THAN 500 WILL BE DEGRADED.
FIGURE 18. TEST CIRCUITS
Figure 18A illustrates the optimum output load for testing AC
performance. Figure 18B illustrates the optimum output load
when connecting to 50 input terminated equipment.
Application Information
General
The ISL59424, ISL59445 are triple 2:1 and 4:1 muxes that are
ideal for the matrix element of high performance switchers and
routers. The ISL59424, ISL59445 are optimized to drive a
1.5pF in parallel with a 500 load. The capacitance can be
split between the PCB capacitance an and external load
capacitance. Their low input capacitance and high input
resistance provide excellent 50 or 75 terminations.
Ground Connections
For the best isolation and crosstalk rejection, all GND pins and
NIC pins must connect to the GND plane.
Control Signals
S0, S1, ENABLE, LE, HIZ - These pins are binary coded,
TTL/CMOS compatible control inputs. The S0, S1 pins select
which one of the inputs connect to the output. All three amplifiers
are switched simultaneously from their respective inputs. The
ENABLE, LE, HIZ pins are used to disable the part to save
power, latch in the last logic state and three-state the output
amplifiers, respectively. For control signal rise and fall times less
than 10ns the use of termination resistors close to the part
should be considered to minimize transients coupled to the
output.
Power-Up Considerations
The ESD protection circuits use internal diodes from all pins
the V+ and V- supplies. In addition, a dV/dT- triggered clamp is
connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 section of the “Pin
Descriptions” on page 8. The dV/dT triggered clamp imposes a
maximum supply turn-on slew rate of 1V/µs. Damaging
currents can flow for power supply rates-of-rise in excess of
1V/µs, such as during hot plugging. Under these conditions,
additional methods should be employed to ensure the rate of
rise is not exceeded.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic input
pins. Schottky diodes (Motorola MBR0550T or equivalent)
connected from V+ to ground and V- to ground (Figure 19) will
shunt damaging currents away from the internal V+ and V-
ESD diodes in the event that the V+ supply is applied to the
device before the V- supply.
If positive voltages are applied to the logic or analog video
input pins before V+ is applied, current will flow through the
internal ESD diodes to the V+ pin. The presence of large
decoupling capacitors and the loading effect of other circuits
connected to V+, can result in damaging currents through the
ESD diodes and other active circuits within the device.
Therefore, adequate current limiting on the digital and analog
inputs is needed to prevent damage during the time the
voltages on these inputs are more positive than V+.
FN7456 Rev 3.00
September 30, 2011
Page 9 of 14
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