W78C51DP-40 데이터 시트보기 (PDF) - Winbond
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W78C51DP-40 Datasheet PDF : 18 Pages
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Preliminary W78C51D
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will
usually experience less than a ±20 nS variation. The numbers below represent the performance
expected from a 0.5 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
TCH
TCL
F OP, TCP
PARAMETER
SYMBOL
MIN.
Operating Speed
FOP
0
Clock Period
TCP
25
Clock High
TCH
10
Clock Low
TCL
10
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
TYP.
-
-
-
-
MAX.
40
-
-
-
UNIT
MHz
nS
nS
nS
NOTES
1
2
3
3
Program Fetch Cycle
PARAMETER
SYMBOL MIN.
Address Valid to ALE Low
TAAS
1 TCP-∆
Address Hold from ALE Low
TAAH
1 TCP-∆
ALE Low to PSEN Low
TAPL
1 TCP-∆
PSEN Low to Data Valid
TPDA
-
Data Hold after PSEN High
TPDH
0
Data Float after PSEN High
TPDZ
0
ALE Pulse Width
TALW
2 TCP-∆
PSEN Pulse Width
TPSW
3 TCP-∆
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "∆" (due to buffer driving delay and wire loading) is 20 nS.
TYP.
-
-
-
-
-
-
2 TCP
3 TCP
MAX.
-
-
-
2 TCP
1 TCP
1 TCP
-
-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
NOTES
4
1, 4
4
2
3
4
4
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Publication Release Date: January 1999
Revision A1
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