HI5701(2005) 데이터 시트보기 (PDF) - Intersil

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HI5701
(Rev.:2005)

6-Bit, 30MSPS, Flash A/D Converter

Intersil 

HI-5701

Electrical Specifications VDD = +5.0V; VREF+ = +4.0V; VREF- = VSS = GND; fS = Specified Clock Frequency at 50% Duty Cycle;

CL = 30pF; Unless Otherwise Specified (Continued)

25oC

(NOTE 3)

0oC TO 70oC

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

MAX UNITS

Analog Input Bias Current, IB

REFERENCE INPUTS

VIN = 0V, 4V

-

0.01

±1.0

-

±1.0

µA

Total Reference Resistance, RL

Reference Resistance Tempco, TC

DIGITAL INPUTS

250

370

-

235

-

Ω

-

+0.266

-

-

-

Ω/oC

Input Logic High Voltage, VIH

Input Logic Low Voltage, VIL

Input Logic High Current, IIH

Input Logic Low Current, IIL

Input Capacitance, CIN

DIGITAL OUTPUTS

VIN = 5V

VIN = 0V

2.0

-

-

2.0

-

V

-

-

0.8

-

0.8

V

-

-

1.0

-

1.0

µA

-

-

1.0

-

1.0

µA

-

7

-

-

-

pF

Output Logic Sink Current, IOL

Output Logic Source Current, IOH

Output Leakage, IOFF

Output Capacitance, COUT

TIMING CHARACTERISTICS

VO = 0.4V

VO = 4.5V

CE2 = 0V

CE2 = 0V

3.2

-

-

3.2

-

mA

-3.2

-

-

-3.2

-

mA

-

-

±1.0

-

±1.0

µA

-

5.0

-

-

-

pF

Aperture Delay, tAP

Aperture Jitter, tAJ

Data Output Enable Time, tEN

Data Output Disable Time, tDIS

Data Output Delay, tOD

Data Output Hold, tH

POWER SUPPLY REJECTION

(Note 3)

(Note 3)

(Note 3)

(Note 3)

-

6

-

-

-

ns

-

30

-

-

-

ps

-

12

20

-

20

ns

-

11

20

-

20

ns

-

14

20

-

20

ns

5

10

-

5

-

ns

Offset Error PSRR, ∆VOS

Gain Error PSRR, ∆FSE

POWER SUPPLY CURRENT

VDD = 5V ±10%

VDD = 5V ±10%

-

±0.1

±1.0

-

±1.5

LSB

-

±0.1

±1.0

-

±1.5

LSB

Supply Current, IDD

fS = 20MHz

-

50

60

-

75

mA

NOTE:

3. Parameter guaranteed by design or characterization and not production tested.

4

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