HI5701(2005) 데이터 시트보기 (PDF) - Intersil
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HI5701 Datasheet PDF : 12 Pages
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HI-5701
TABLE 1. PIN DESCRIPTIONS
PIN # NAME
DESCRIPTION
1 D5
Bit 6, Output (MSB).
2 OVF
Overflow, Output.
3
VSS
4 NC
Digital Ground.
No Connection.
5 CE2
Three-State Output Enable Input, Active
High (See Table 2).
6 CE1
Three-State Output Enable Input, Active
Low (See Table 2).
7 CLK
Clock Input.
8 PHASE
Sample Clock Phase Control Input. When
Phase is Low, Sample Unknown (φ1) Oc-
curs When the Clock is Low and Auto Bal-
ance (φ2) Occurs When the Clock is High
(See Text).
9
VREF +
10 VREF-
11 VIN
12 VDD
13 D0
Reference Voltage Positive Input.
Reference Voltage Negative Input.
Analog Signal Input.
Power Supply, +5V.
Bit 1, Output (LSB).
14 D1
Bit 2, Output.
15 D2
16 1/2 R2
17 D3
Bit 3, Output.
Reference Ladder Midpoint.
Bit 4, Output.
18 D4
Bit 5, Output.
TABLE 2. CHIP ENABLE TRUTH TABLE
CE1
CE2
D0 - D5
OVF
0
1
Valid
Valid
1
1
Three-State
Valid
X
0
Three-State
Three-State
X = Don’t Care
Theory of Operation
The HI-5701 is a 6-bit analog-to-digital converter based on a
parallel CMOS “flash” architecture. This flash technique is an
extremely fast method of A/D conversion because all bit
decisions are made simultaneously. In all, 64 comparators
are used in the HI-5701; 63 comparators to encode the
output word, plus an additional comparator to detect an
overflow condition.
The CMOS HI-5701 works by alternately switching between
a “Sample” mode and an “Auto Balance” mode. Splitting up
the comparison process in this CMOS technique offers a
number of significant advantages. The offset voltage of each
CMOS comparator is dynamically canceled with each
conversion cycle such that offset voltage drift is virtually
eliminated during operation. The block diagram and timing
diagram illustrate how the HI-5701 CMOS flash converter
operates.
The input clock which controls the operation of the HI-5701
is first split into a non-inverting φ1 clock and an inverting φ2
clock. These two clocks, in turn, synchronize all internal
timing of analog switches and control logic within the
converter.
In the “Auto Balance” mode (φ1), all φ1 switches close and
φ2 switches open. The output of each comparator is
momentarily tied to its own input, self-biasing the comparator
midway between VSS and VDD and presenting a low
impedance to a small input capacitor. Each capacitor, in turn,
is connected to a reference voltage tap from the resistor
ladder. The Auto Balance mode quickly precharges all 64
input capacitors between the self-bias voltage and each
respective tap voltage.
In the “Sample” mode (φ2), all φ1 switches open and φ2
switches close. This places each comparator in a sensitive
high gain amplifier configuration. In this open loop state, the
input impedance is very high and any small voltage shift at
the input will drive the output either high or low. The φ2 state
also switches each input capacitor from its reference tap to
the input signal. This instantly transfers any voltage
difference between the reference tap and input voltage to the
comparator input. All 64 comparators are thus driven
simultaneously to a defined logic state. For example, if the
input voltage is at mid-scale, capacitors precharged near
zero during φ1 will push comparator inputs higher than the
self bias voltage at φ2; capacitors precharged near the
reference voltage push the respective comparator inputs
lower than the bias point. In general, all capacitors
precharged by taps above the input voltage force a “low”
voltage at comparator inputs; those precharged below the
input voltage force “high” inputs at the comparators.
During the next φ1 state, comparator output data is latched
into the encoder logic block and the first stage of encoding
takes place. The following φ2 state completes the encoding
process. The 6 data bits (plus overflow bit) are latched into
the output flip-flops at the next falling clock edge. The
Overflow bit is set if the input voltage exceeds VREF+ - 1/2
LSB. The output bus may be either enabled or disabled
according to the state of CE1 and CE2 (See Table 2). When
disabled, output bits assume a high impedance state.
As shown in the timing diagram, the digital output word
becomes valid after the second φ1 state. There is thus a one
and a half cycle pipeline delay between input sample and
digital output. “Data Output Delay” time indicates the slight
time delay for data to become valid at the end of the φ1 state.
Refer to the Glossary of Terms for other definitions.
8
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