HI5701(2005) 데이터 시트보기 (PDF) - Intersil
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HI5701 Datasheet PDF : 12 Pages
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HI-5701
CLOCK
INPUT
50Ω
D5
OVF
VSS
+5V
CE2
CE1
CLK
+4V
10µF
0.01µF
PHASE
VREF+
D4
D3
1/2R
NC
D2
D1
D0
VDD
0.01µF
DATA
OUPUT
+5V
10µF
+9V to +12V
VIN
VREF-
0.01µF
100Ω HA-5033
10µF
50Ω
ANALOG
SIGNAL
INPUT
0.01µF
-9V to -12V
10µF
FIGURE 13. TEST CIRCUIT
Application Information
Voltage Reference
The reference voltage is applied across the resistor ladder at
the input of the converter, between VREF+ and VREF-. In
most applications, VREF- is simply tied to analog ground
such that the reference source drives VREF+. The reference
must be capable of supplying enough current to drive the
minimum ladder resistance of 235Ω over temperature.
The HI-5701 is specified for a reference voltage of 4.0V, but
will operate with voltages as high as the VDD supply. In the
case of 4.0V reference operation, the converter encodes the
analog input into a binary output in LSB increments of
(VREF+ -VREF)/64, or 62.5mV. Reducing the reference
voltage reduces the LSB size proportionately and thus
increases linearity errors. The minimum practical reference
voltage is about 2V. Because the reference voltage terminals
are subjected to internal transient currents during
conversion, it is important to drive the reference pins from a
low impedance source and to decouple thoroughly. Again,
ceramic and tantalum (0.01µF and 10µF) capacitors near
the package pin are recommended. It is not necessary to
decouple the 1/2R tap point pin for most applications.
It is possible to elevate VREF- from ground if necessary. In
this case, the VREF- pin must be driven from a low
impedance reference capable of sinking the current through
the resistor ladder. Careful decoupling is again
recommended.
Digital Control and Interface
The HI-5701 provides a standard high speed interface to
external CMOS and TTL logic families. Four digital inputs are
provided to control the function of the converter. The clock
and phase inputs control the sample and auto balance
modes. The digital outputs change state on the clock phase
which begins the sample mode. Two chip enable inputs
control the three-state outputs of output bits D0 through D5
and the Overflow OVF bit. As indicated in Table 2, all output
bits are high impedance when CE2 is low, and output bits D0
through D5 are independently controlled by CE1.
Although the Digital Outputs are capable of handling typical
data bus loading, the bus capacitance charge/discharge
currents will produce supply and local ground disturbances.
Therefore, an external bus driver is recommended.
Clock
The clock should be properly terminated to digital ground
near the clock input pin. Clock frequency defines the
conversion frequency and controls the converter as
described in the “Theory of Operation” section. The Auto
Balance φ1 half cycle of the clock may be reduced to 16ns;
the Sample φ2 half cycle may be varied from a minimum of
16ns to a maximum of 8µs.
TABLE 3. PHASE CONTROL
CLOCK
0
PHASE
0
INTERNAL GENERATION
Sample Unknown (φ2)
0
1
Auto Balance (φ1)
1
0
Auto Balance (φ1)
1
1
Sample Unknown (φ2)
Gain and Offset Adjustment
In applications where accuracy is of utmost importance,
three adjustments can be made; i.e., offset, gain, and
9
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