ADP122 데이터 시트보기 (PDF) - Analog Devices

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ADP122

5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator

Analog Devices 

ADP122/ADP123

OUTLINE DIMENSIONS

2.90 BSC

1.60 BSC

5

4

1

2

3

2.80 BSC

*0.90 MAX

0.70 MIN

1.90

BSC

0.95 BSC

*1.00 MAX 0.20

0.08

0.10 MAX

0.50

0.30

8°

SEATING

4°

0.60

PLANE

0°

0.45

0.30

*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH

THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.

Figure 54. 5-Lead Thin Small Outline Transistor Package [TSOT]

(UJ-5)

Dimensions shown in millimeters

PIN 1 INDEX

AREA

0.60

0.55

0.50

SEATING

PLANE

2.00

BSC SQ

1.70

1.60

1.50

4

0.65 BSC

6

0.175 REF

TOP VIEW

0.425

0.350

0.275

EXPOSED

PAD

1.10

1.00

0.90

3

1

BOTTOM VIEW

PIN 1

INDICATOR

(R 0.15)

0.05 MAX

0.02 NOM

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

0.35

0.30

0.20 REF

0.25

Figure 55. 6-Lead Lead Frame Chip Scale Package [LFCSP_UD]

2.00 mm× 2.00 mm Body, Ultra Thin, Dual Lead

(CP-6-3)

Dimensions shown in millimeters

Data Sheet

Rev. E | Page 20 of 24

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