74LVQ174(1998) 데이터 시트보기 (PDF) - Fairchild Semiconductor
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74LVQ174 Datasheet PDF : 6 Pages
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Functional Description
Truth Table
The LVQ174 consists of six edge-triggered D flip-flops with
individual D inputs and Q outputs. The Clock (CP) and Mas-
ter Reset (MR) are common to all flip-flops. Each D input’s
Inputs
MR
CP
D
state is transferred to the corresponding flip-flop’s output fol-
L
X
X
lowing the LOW-to-HIGH Clock (CP) transition. A LOW input
to the Master Reset (MR) will force all outputs LOW indepen-
dent of Clock or Data inputs. The LVQ174 is useful for appli-
H
N
H
H
N
L
cations where the true output only is required and the Clock
H
L
X
and Master Reset are common to all storage elements.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N = LOW-to-HIGH Transition
Logic Diagram
Output
Q
L
H
L
Q
DS011353-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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