LB1975 데이터 시트보기 (PDF) - SANYO -> Panasonic

부품명

상세내역

제조사

LB1975

3-phase Brushless Motor Driver

SANYO -> Panasonic 

IC Description

LB1975

1. Direct PWM Drive

The LB1975 employs the direct PWM drive principle. Motor rotation speed is controlled by varying the output duty

cycle according to an analog voltage input (VCTL). This eliminates the need to alter the motor power supply voltage.

Compared to previous ICs using the PAM principle (such as the Sanyo LB1690), this allows simplification of the

power supply circuitry. The VCTL input can be directly supplied by a microcontroller, motor speed can, therefore, be

controlled directly from the microcontroller.

For PWM, the source-side output transistors are switched on and off so that the ON duty tracks the VCTL input. The

output duty cycle can be controlled over the range of 0% to 100% by the VCTL input.

2. PWM Frequency

The PWM oscillator frequency fPWM [Hz] is set by the capacitance C [pF] connected between the OSC pin and GND.

The following equation applies:

fPWM ≈ 1 / (1.97 × C) × 108

Because output transistor on/off switching is subject to a delay, setting the PWM frequency to a very high value will

cause the delay to become noticeable. The PWM frequency therefore should normally be kept below 40kHz (typ.),

which is achieved with a capacitance C of 1300pF or higher. For reference, the source-side output transistor switching

delay time is about 2µs for ON and about 4µs for OFF.

3. Output Diodes

Because the PWM switching operation is carried out by the source-side output transistors, Schottky barrier diodes must

be connected between the OUT pins and GND (OUT1 to OUT3). Use diodes with an average forward current rating in

the range of 1.0 to 2.0A, in accordance with the motor type and current limiting requirements.

If no Schottky barrier diodes are connected externally, or if Schottky barrier diodes with high forward voltage (VF) are

used, the internal parasitic diode between OUT and GND becomes active. When this happens, the output logic circuit

may malfunction, resulting in feed-through current in the output which can destroy the output transistors. To prevent

this possibility, Schottky barrier diodes must be used and dimensioned properly.

The larger the VF of the externally connected Schottky barrier diodes, or the hotter the IC is, the more likely are the

parasitic diodes between OUT and GND to become active and the more likely is malfunction to occur. The VF of the

Schottky barrier diodes must be determined so that output malfunction does not occur also when the IC becomes hot. If

malfunction occurs, choose a Schottky barrier diode with lower VF.

4. Protection circuits

4-1. Low voltage protection circuit

When the VCC voltage falls below a stipulated level (VLVSD), the low voltage protection circuit cuts off the

source-side output transistors to prevent VCC related malfunction.

4-2. Thermal shutdown circuit (overheat protection circuit)

When the junction temperature rises above a stipulated value (TSD), the thermal shutdown circuit cuts off the

sourceside output transistors to prevent IC damage due to overheating. Design the application heat characteristics so

that the protection circuit will not be triggered under normal circumstances.

4-3. Current limiter

The current limiter cuts off the source-side output transistors when the output current reaches a preset value (limiter

value). This interrupts the source current and thereby limits the output current peak value. By connecting the

resistance Rf between the RF pin and ground, the output current can be detected as a voltage. When the RF pin

voltage reaches 0.5V (typ.), the current limiter is activated. It performs on/off control of the source-side output

transistors, thereby limiting the output current to the value determined by 0.5/Rf.

5. Hall Input Circuit

The Hall input circuit is a differential amplifier with a hysteresis of 32mV (typ.). The operation DC level must be

within the common-mode input voltage range (1.5V to VCC − 1.5V). To prevent noise and other adverse influences,

the input level should be at least 3 times the hysteresis (120 to 16mVp-p). If noise at the Hall input is a problem, a

noise-canceling capacitor (about 0.01µF) should be connected across the Hall input IN+ and IN− pins.

6. FG Output Circuit

The Hall input signal at IN1, IN2, and IN3 is combined and subject to waveform shaping before being output. The

signal at FG1 has the same frequency as the FG1 Hall input, and the signal at FG2 has a frequency that is three times

higher.

No.6087-8/10

Share Link: