STK15C68(2011) 데이터 시트보기 (PDF) - Cypress Semiconductor
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STK15C68 Datasheet PDF : 17 Pages
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STK15C88
AC Switching Characteristics
SRAM Read Cycle
Parameter
25 ns
45 ns
Cypress
Parameter
Alt
Description
Unit
Min
Max Min Max
tACE
tELQV
Chip Enable Access Time
–
25
–
45
ns
tRC [5]
tAVAV, tELEH
Read Cycle Time
25
–
45
–
ns
tAA [6]
ly. tDOE
n tOHA [6]
o tLZCE [7]
s tHZCE [7]
am tLZOE [7]
r tHZOE [7]
og tPU [4]
pr tPD [4]
tAVQV
tGLQV
tAXQX
tELQX
tEHQZ
tGLQX
tGHQZ
tELICCH
tEHICCL
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
–
25
–
45
–
10
–
20
5
–
5
–
5
–
5
–
–
10
–
15
0
–
0
–
–
10
–
15
0
–
0
–
–
25
–
45
tion Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled [5, 7]
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NoItnreproduc 2(
Figure 6. SRAM Read Cycle 2: CE and OE Controlled [5]
W5&
W/=&(
W$&(
W3'
W+=&(
W'2(
W+=2(
ns
ns
ns
ns
ns
ns
ns
ns
ns
W/=2(
'4 '$7$287
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W38
$&7,9(
,&&
67$1'%<
Notes
5. WE must be HIGH during SRAM Read Cycles and LOW during SRAM WRITE cycles.
6. I/O state assumes CE and OE < VIL and WE > VIH; device is continuously selected.
7. Measured ±200 mV from steady state output voltage.
Document Number: 001-50593 Rev. *C
Page 9 of 17
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