STK15C68 데이터 시트보기 (PDF) - Cypress Semiconductor
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STK15C68 Datasheet PDF : 15 Pages
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STK15C88
AC Switching Characteristics
SRAM Read Cycle
Parameter
Cypress
Parameter
Alt
tACE
tRC [5]
tAA [6]
tDOE
tOHA [6]
tLZCE [7]
tHZCE [7]
tLZOE [7]
tHZOE [7]
tPU [4]
tPD [4]
tELQV
tAVAV, tELEH
tAVQV
tGLQV
tAXQX
tELQX
tEHQZ
tGLQX
tGHQZ
tELICCH
tEHICCL
Switching Waveforms
Description
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
25 ns
Min
Max
25
25
25
10
5
5
10
0
10
0
25
Figure 5. SRAM Read Cycle 1: Address Controlled [5, 7]
W5&
$''5(66
W$$
W2+$
'4 '$7$287
'$7$9$/,'
45 ns
Unit
Min Max
45
ns
45
ns
45
ns
20
ns
5
ns
5
ns
15
ns
0
ns
15
ns
0
ns
45
ns
$''5(66
&(
2(
'4 '$7$287
,&&
Figure 6. SRAM Read Cycle 2: CE and OE Controlled [5]
W5&
W/=&(
W$&(
W3'
W+=&(
W'2(
W/=2(
W38
67$1'%<
$&7,9(
W+=2(
'$7$9$/,'
Notes
5. WE must be HIGH during SRAM Read Cycles and LOW during SRAM WRITE cycles.
6. I/O state assumes CE and OE < VIL and WE > VIH; device is continuously selected.
7. Measured ±200 mV from steady state output voltage.
Document Number: 001-50593 Rev. **
Page 8 of 15
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