FAN53601 데이터 시트보기 (PDF) - ON Semiconductor
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FAN53601 Datasheet PDF : 16 Pages
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Operation Description
The FAN53601/11 is a 6 MHz, step-dow n sw itching voltage
regulator available in 600 mA or 1 A options that delivers a
fixed output from an input voltage supply of 2.3 V to 5.5 V.
Using a proprietary architecture w ith synchronous
rectification, the FA N53601/11 is capable of delivering a
peak efficiency of 92%, w hile maintaining efficiency over
80% at load currents as low as 1 mA.
The regulator operates at a nominal fixed frequency of
6 MHz, w hich reduces the value of the external components
to as low as 470 nH for the output inductor and 4.7 µF for the
output capacitor. In addition, the PWM modulator can be
synchronized to an external frequency source.
Control Scheme
The FAN53601/11 uses a proprietary, non-linear, fixed-
frequency PWM modulator to deliver a fast load transient
response, while maintaining a constant sw itching frequency
over a w ide range of operating conditions. The regulator
performance is independent of the output capacitor ESR,
allow ing for the use of ceramic output capacitors. Although
this type of operation nor mally results in a sw itching frequency
that varies w ith input voltage and load current, an internal
frequency loop holds the sw itching frequency constant over a
large range of input voltages and load currents.
For very light loads, the FAN53601/11 operates in
Discontinuous Current Mode ( DCM) s ingle-pulse PFM Mode,
which produces low output ripple compared w ith other PFM
architectures. Transition betw een PWM and PFM is
seamless, allow ing for a smooth transition betw een DCM
and CCM.
Combined w ith exceptional transient response
characteristics, the very low quiescent current of the
controller maintains high efficiency; even at very light loads;
while preserving fast transient response for applications
requiring tight output regulation.
Enable and Soft-Start
When EN is LOW, all circuits are off and the IC draw s
~250 nA of current. When EN is HIGH and VIN is above its
UVLO threshold, the regulator begins a soft-start cycle. The
output ramp during soft-start is a fixed slew rate of 50 mV/µs
f rom Vout = 0 to 1 V, then 12.5 mV/µs unt il t he output reaches
its setpoint. Regardless of the state of the MODE pin, PFM
Mode is enabled to prevent current from being discharged
from COUT if soft-start begins w hen COUT is charged.
In addition, all voltage options can be ordered w ith a feature
that actively discharges FB to ground through a 230 Ω path
when EN is LOW. Raising EN above its threshold voltage
activates the part and starts the soft-start cycle. During soft-
start, the internal reference is ramped using an exponential
RC shape to prevent overshoot of the output voltage. Current
limiting minimizes inrush during soft-start.
The current-limit fault response protects the IC in the event
of an over-current condition present dur ing soft-start. As a
result, the IC may fail to start if heavy load is applied during
startup and/or if excessive COUT is used.
The current required to charge COUT during soft-start
commonly referred to as “displacement current” is given as:
IDISP
= COUT
•
dV
dt
(1)
dV
w here refers to the soft-start slew rate.
dt
To prevent shut dow n during soft-start, the follow ing condition
must be met:
IDISP + ILOAD < IMAX(DC)
(2)
w here IMAX(DC) is the maximum load current the IC is
guaranteed to support.
Startup into Large COUT
Multiple soft-start cycles are required for no-load startup if
COUT is greater than 15 µF. Large COUT requires light initial
load to ensure the FA N53601/11 starts appropr iately. The IC
shuts dow n for 1.3 ms w hen IDISP exceeds ILIMIT for more
than 200 µs of current limit. The IC then begins a new soft-
start cycle. Since COUT retains its charge w hen the IC is off,
the IC reaches regulation after multiple soft-start attempts.
M ODE Pin
Logic 1 on this pin forces the IC to stay in PWM Mode. A
logic 0 allow s the IC to automatically sw itch to PFM during
light loads. If the MODE pin is toggled w ith a frequency
betw een 1.3 MHz and 1.7 MHz, the converter synchronizes
its sw itching frequency to four times the frequency on the
MODE pin.
The MODE pin is internally buffered w ith a Schmitt trigger,
w hich allow s the MODE pin to be driven w ith slow rise and
fall times. An asy mmetric duty cycle for frequency
synchronization is also per mitted as long as the minimum
time below VIL(MAX) or above VIH(MAX) is 100 ns.
Current Limit, Fault Shutdown, and Restart
A heavy load or short circuit on the output causes the current
in the inductor to increase until a maximum current threshold
is reached in the high-side sw itch. Upon reaching this point,
the high-side sw itch turns off, preventing high currents from
causing damage. The regulator continues to limit the current
cycle-by-cycle. After 16 cycles of current limit, the regulator
triggers an over-current fault, causing the regulator to shut
dow n f or about 1.3 ms before attempting a restart.
If the fault is caused by short circuit, the soft-start circuit
attempts to restart and produces an over-current fault after
about 200 µs, w hich results in a duty cycle of less than 15%,
limiting pow er dissipation.
The closed- loop peak-current limit is not the same as the
open-loop tested current limit, ILIM(OL), in the Electrical
Characteristics table. This is primar ily due to the effect of
propagation delays of the IC current limit comparator.
Unde r-Voltage Lockout (UVLO)
When EN is HIGH, the under-voltage lockout keeps the part
from operating until the input supply voltage r ises high
enough to properly operate. This ensures no misbehavior of
the regulator during startup or shutdown.
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