TP6800 데이터 시트보기 (PDF) - Topro

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TP6800

Digital Video Camera Controller

Topro 

TP6800

Digital Video Camera Controller

(USB interface / JPEG compression / Video processing)

B7 : SNAP shot button

B6 : Power LED(indicator)

B5 : reserved

B4 : Descriptor selector of internal mask rom.

(0: Bank 1， 1: Bank 2)

B3 : Before USB SET the device configured, this pin is

used as the selector of internal ROM(0) or external

EEPROM(1) by connecting a 50KΩ(5V) resistor to

pull-up/pull-down . Once the device has been

configured by USB command, this port could work as a

general-purpose programmable I/O.

B2, B1, B0 : Selector of the CMOS sensor bank.

1.2 System related registers:

Address Name

21 ENDP_1_CTL

(endpoint 1 control

register)

attribute

W

22 ENDP1_MAX_PackSize W

Note :

The value of this register

also could be set by usb

command "Set Interface",

And read by usb

command "get Interface".

Descriptions

Bit[0]: Enable bit for endpoint 1 to begin send data.(1:

enable，0:disable)

Bit[1]: Enable bit for chip internal Timing generator.(1:

enable to generate timing signals,

0: disable all the timing sequence signals)

Bit[2-7]: reserved.

Bit 2/Bit 1/Bit 0 :

000 : Max_PackSize of endpoint 1 is 0.(Default)

001 : Max_PackSize of endpoint 1 is 128

010 : Max_PackSize of endpoint 1 is 256

011 : Max_PackSize of endpoint 1 is 512

100 : Max_PackSize of endpoint 1 is 640

101 : Max_PackSize of endpoint 1 is 768

110 : Max_PackSize of endpoint 1 is 1023

Bit3 - bit7 : reserved.

1.3 Timing Generator related registers

Address Name

attribute

2F Timing_CFG

W

Default value : 0Ch

Descriptions

Bit[0] : PCLK direction

(1: input from sensor，

0: generated by TP6800)

Bit[1] : HSYNC/VSYNC direction control

(0: output，1: input from sensor)

Bit[2] : HSYNC/VSYNC Polarity(1: Active

high, 0: Active low)

Bit[3] : PCLK2MCLK.(1: Generated PCLK

has same phase with MCLK,

otherwise they have different phase)

Page 11 of 33

TOPRO CONFIDNETIAL

2003/7/4 Print

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