HD74CDCV857A 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics
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HD74CDCV857A Datasheet PDF : 13 Pages
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HD74CDCV857A
Switching Characteristics
Item
Symbol Min Typ Max Unit Test Conditions Notes
Period jitter
t
PER
Half period jitter
tHPER
Cycle to cycle jitter
tCC
Static phase offset
tSPE
Output clock skew
t
sk
Operating clock frequency f
CLK(O)
Application clock
frequency
fCLK(A)
–75 —
–100 —
–75 —
–50 —
—
—
60
—
80
—
75
ps
See figure 6, 9 7, 8
100 ps
See figure 7, 9 8, 10
75
ps
See figure 5, 9 10
50
ps
See figure 3, 9 4, 5, 9, 10
100 ps
See figure 4, 9
170 MHz See figure 9
1, 2
170 MHz See figure 9
1, 3
Input clock duty cycle
tDC
40
—
60
%
10
Output clock Slew rate tSL(O)
1.0
—
2.0
V/ns See figure 9
20% – 80%
PLL stabilization time
tSTAB
—
—
0.1
ms
See figure 9
6, 10
SSC modulation
30
—
50
KHz
10
frequency
SSC clock input
0.00 —
–0.50 %
10
frequency deviation
PLL loop bandwidth
2
—
—
MHz
10
Phase angle
—
—
–0.031 degrees
10
Notes: 1. The PLL must be able to handle spread spectrum induced skew (the specification for this
frequency modulation can be found in the latest Intel PC100 Registered DIMM specification)
2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in
which it is not required to meet the other timing parameters.
3. Application clock frequency indicates a range over which the PLL must meet all timing
parameters.
4 Assumes equal wire length and loading on the clock output and feedback path.
5. Static phase offset does not include jitter.
6. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its
feedback signal to its reference signal after power up.
7. Period jitter defines the largest variation in clock period, around anominal clock period.
8. Period jitter and half period jitter are independent from each other.
9. Conditions at V = 2.5 V, Ta = 25°C.
DDQ
10. Guaranteed by design, not 100% tested in production.
Rev.1 Jun. 2002 page 8 of 13
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